Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2000-09-18
2002-06-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S241000, C438S618000, C438S636000, C438S689000, C438S786000
Reexamination Certificate
active
06399424
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a contact structure and more particularly to formation of a buried wiring and a low dielectric constant interlayer insulating film.
2. Description of the Background Art
In order to implement an increase in a speed in a semiconductor device having a small gate length (0.18 &mgr;m or less, for example), it is important that a signal delay in the device should be reduced. The signal delay in the device is represented by the sum of a signal delay in a transistor and a signal delay in a wiring. As a reduction in a wiring pitch is advanced rapidly, the signal delay in the wiring occupies a greater part of the signal delay in the device than the signal delay in the transistor.
The signal delay in the wiring is proportional to a product of a resistance of the wiring and a capacitance between the wirings. Therefore, it is necessary to decrease the resistance of the wiring or the capacitance between the wirings, thereby reducing the signal delay in the wiring. In order to solve this problem, there has vigorously been studied a combination of a buried wiring technique using a metal having a low resistance such as copper and a technique for forming an interlayer insulating film having a lower dielectric constant than that of a silicon oxide film to be a conventional typical interlayer insulating film. The present invention relates to a method of manufacturing a contact structure having a combination of a buried wiring forming method (a so-called Dual Damascene process) of forming a connecting hole for a lower layer wiring and an upper layer wiring at a time and formation of an organic low dielectric constant interlayer insulating film.
FIGS. 7
to
19
typically show each step of a conventional method of manufacturing a contact structure in which the formation of the buried wiring and that of the low dielectric constant interlayer insulating film are combined.
FIGS. 14
to
17
are single view drawings for easily distinguishing a connecting hole from a wiring trench.
As shown in
FIG. 7
, first of all, an element such as a transistor is formed on a semiconductor substrate
1
such as a silicon substrate, and an insulating film is then formed to cover the element. In
FIG. 7
, the element and the insulating film are collectively represented as a lower insulating layer
2
and the element is not shown.
Next, a first low dielectric constant interlayer insulating film
3
is formed on the lower insulating layer
2
, and a hard mask
4
is formed on the first low dielectric constant interlayer insulating film
3
. A polyarylether (hereinafter referred to as PAE) film to be an organic substance comprising carbon, oxygen and hydrogen as main components, for example, is employed as the first low dielectric constant interlayer insulating film
3
and a silicon oxide film is employed as the hard mask
4
, for example.
A photoresist
16
is formed on the hard mask
4
and a pattern
17
a
of the wiring trench is formed by using a photolithographic technique (FIG.
8
). Then, the hard mask
4
is subjected to etching by using the photoresist
16
as a mask so that a pattern
17
b
of the wiring trench is formed in the hard mask
4
(FIG.
9
). In the case in which the silicon oxide film is employed as the hard mask
4
, etching is carried out through plasma etching using a mixed gas of CF
4
and O
2
, for example.
After the etching for the hard mark
4
is completed, the first low dielectric constant interlayer insulating film
3
is subjected to the etching to form a wiring trench
17
c
. In the case in which the PAE film is employed as the first low dielectric constant interlayer insulating film
3
, plasma etching using a mixed gas of O
2
and N
2
is carried out, for example. An etching gas has an etching effect for the photoresist. Therefore, the photoresist
16
can also be removed at the same time that the first low dielectric constant interlayer insulating film
3
is to be etched (FIG.
10
). In this case, the hard mask
4
prevents the first low dielectric constant interlayer insulating film
3
in a portion other than an opening of the pattern
17
b
from being etched after the photoresist
16
is completely removed. For example, since the silicon oxide film is not removed by the plasma etching using the mixed gas of O
2
and N
2
, it is suitable for the hard mask
4
.
Then, a barrier metal (not shown) is formed over the whole surface of the semiconductor substrate
1
by using a sputtering method, for example, and a first metal film
5
such as copper is formed on the barrier metal by using the sputtering method, a chemical vapor deposition (hereinafter referred to as CVD) process, an electrolytic plating method or the like (FIG.
11
), for example. The barrier metal is provided to prevent a metal constituting the first metal film
5
from being diffused into the lower insulating layer
2
and the first low dielectric constant interlayer insulating film
3
.
Then, the barrier metal and the first metal film
5
which are provided above a surface of the hard mark
4
are removed by using a chemical mechanical polishing (which will be hereinafter referred to as CMP) process, for example. The barrier metal and the first metal film
5
are caused to remain only in the wiring trench (FIG.
12
).
Next, a first interlayer insulating film
6
, a second low dielectric constant interlayer insulating film
7
, a second interlayer insulating film
8
, a third low dielectric constant interlayer insulating film
9
and a third interlayer insulating film
10
are formed on the hard mask
4
and the first metal film
5
in this order (FIG.
13
). For example, a silicon nitride film is employed as the first interlayer insulating film
6
, a silicon oxide film is employed as the second and third interlayer insulating films
8
and
10
, and a PAE film is employed as the second and third low dielectric constant interlayer insulating films
7
and
9
.
Subsequently, a photoresist
18
is formed on the third interlayer insulating film
10
and a pattern
15
e
of a connecting hole is formed in the photoresist
18
by the photolithographic technique (FIG.
14
). Then, the third interlayer insulating film
10
, the third low dielectric constant interlayer insulating film
9
, the second interlayer insulating film
8
and the second low dielectric constant interlayer insulating film
7
are subjected to etching by using the photoresist
18
as a mask so that a connecting hole
15
f
is formed (FIG.
15
). In the case in which the silicon oxide film is employed as the second and third interlayer insulating films
8
and
10
and the PAE film is employed as the second and third low dielectric constant interlayer insulating films
7
and
9
, it is preferable that the silicon oxide film should be subjected to the plasma etching using the mixed gas of CF
4
and O
2
and the PAE film should be subjected to the plasma etching using the mixed gas of O
2
and N
2
. Moreover, the photoresist
18
is removed at the same time that the PAE film is etched. Furthermore, the first interlayer insulating film
6
functions as an etching stopper during the formation of the connecting hole
15
f
. Accordingly, the first metal film
5
is not etched.
Next, a wiring trench is formed in the third low dielectric constant interlayer insulating film
9
. For this purpose, a photoresist
19
is formed on the third interlayer insulating film
10
and a pattern
13
d
of the wiring trench is formed by the photolithographic technique (FIG.
16
). Then, the third interlayer insulating film
10
and the third low dielectric constant interlayer insulating film
9
are subjected to etching by using the photoresist
19
as a mask so that a pattern
13
e
of the wiring trench is formed. Subsequently, the first interlayer insulating film
6
is subjected to the etching so that a pattern
15
g
of the connecting hole is formed (FIG.
17
). Then, a barrier metal (not shown) is formed over the whole surface of the semiconductor substrate
Goto Kinya
Matsuura Masazumi
Morimoto Noboru
Anya Igwe U.
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Smith Matthew
LandOfFree
Method of manufacturing contact structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing contact structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing contact structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2901499