Method of manufacturing CMOS semiconductor device having decreas

Details Method of manufacturing CMOS semiconductor device having decreas Method of manufacturing CMOS semiconductor device having decreas

1989-12-14

1991-12-24

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 40, 437 45, 437 57, 357 44, H01L 21265

Patent

active

050752421

ABSTRACT:
A method of manufacturing a CMOS semiconductor device includes the step of preparing a substrate having a first region of a second conductivity type serving as prospective source and drain formation regions of a transistor of a first conductivity type, and a second region of the first conductivity type serving as a prospective channel formation region of a transistor of the second conductivity type. The method of manufacturing the device further includes the steps of simultaneously doping an impurity of the first conductivity type having a first concentration in a first depth of each of the first and second regions, and doping an impurity of the first conductivity type having a concentration higher than the first concentration in a second depth smaller than the first depth of the first region.

REFERENCES:
patent: 4530150 (1985-06-01), Shirato
patent: 4553315 (1985-11-01), McCarty
patent: 4697148 (1987-09-01), Komori et al.
patent: 5021356 (1991-06-01), Henderson et al.

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