Method of manufacturing CMOS devices

Details Method of manufacturing CMOS devices Method of manufacturing CMOS devices

1984-07-27

1986-03-25

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 357 239, 357 42, H01L 21265, H01L 2132

Patent

active

045773912

ABSTRACT:
A CMOS semiconductor structure having insulation sidewall spacers whose width is selected independently for NMOS and PMOS devices. The width of the spacer is selected to reduce hot electron injection in the N channel device and to insure that the gate and source regions are aligned with or underlap the gate in the P channel device. A narrower spacer is used for the P channel device than for the N channel device which permits the formation of a P channel device having a threshold voltage less than 1 volt.

REFERENCES:
patent: 3865654 (1975-02-01), Chang et al.
patent: 4234362 (1980-11-01), Riseman
patent: 4397077 (1983-08-01), Derbenwick et al.

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