Method of manufacturing chip integrated substrate

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support

Reexamination Certificate

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Details

C438S127000, C257S724000, C257S790000, C257SE23126, C257S686000, C257S690000, C257SE21504

Reexamination Certificate

active

07807510

ABSTRACT:
There are provided the steps of connecting a chip component13to a first substrate10through a wire14, providing an electrode21on a second substrate20, attaching, to the first substrate10, a molding tool30having a protruded portion31formed corresponding to an array of a bump connecting pad12of the first substrate10and a cavity32formed corresponding to a region in which the chip component13is mounted, thereby forming a first sealing resin34for sealing the chip component13and the wire14, bonding the electrode21to the bump connecting pad12through a solder, thereby bonding the first substrate10to the second substrate20, and filling a second filling resin40in a clearance portion between the first substrate10and the second substrate20.

REFERENCES:
patent: 5973393 (1999-10-01), Chia et al.
patent: 6762078 (2004-07-01), Shin et al.
patent: 2004/0222508 (2004-11-01), Aoyagi
patent: 2006/0071330 (2006-04-01), Suminoe et al.
patent: 2006/0231939 (2006-10-01), Kawabata et al.
patent: 2007/0187810 (2007-08-01), Mok et al.
patent: 2008/0211078 (2008-09-01), Kwon et al.
patent: 2003-347722 (2003-12-01), None

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