Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-01-29
2001-08-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C356S243400, C356S243600
Reexamination Certificate
active
06274396
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to analysis tools used in the processes for the manufacture of semiconductor devices. More specifically, this invention relates to determining the sensitivity of the scan tools used in the manufacture of semiconductor devices. Even more specifically, this invention relates to a method of manufacturing calibration wafers to determine the sensitivity of scan tools used in the manufacture of semiconductor devices.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect or defects increases the cost of the remaining usable chips because the cost of manufacturing the wafer must be apportioned to the number of good chips that can be sold to consumers.
A single semiconductor chip can require numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits.
After many of these process steps, the wafer is placed in a scan tool that detects defects. As the semiconductor devices have become smaller, the size of defects that are or can be “killer” defects has also become smaller. Because of this, it has become increasingly important and critical that the smaller size defects can be accurately detected. However, it has been found that each scan tool has a different sensitivity (calibration) at the lower end, that is, each scan tool can “just” detect different size defects.
Therefore, what is needed is an accurate method of determining the sensitivity of each scan tool in order to determine the smallest size of defects that the scan tool can accurately detect.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by a method of manufacturing calibration wafers that allow an accurate determination of the sensitivity of in-line scan tools.
In accordance with a first aspect of the invention, a first layer of a material is formed on a layer of a substrate material. Calibration spheres are deposited on the first layer of material followed by an etch process that removes exposed portions of the first layer of material. The calibration spheres are removed leaving pillars of the first layer of material formed on the layer of substrate material. The calibration spheres can be of various sizes forming pillars of various sizes. The calibration wafer is run through a scan tool to determine the sensitivity of the scan tool.
In accordance with another aspect of the invention, a layer of a second material is deposited on and around the various size pillars forming bumps over the various size pillars. The calibration wafer is then run through a scan tool to determine the sensitivity of the scan tool.
In accordance with another aspect of the invention, a layer of material is formed on a layer of a substrate, a layer of photoresist is formed on the layer of material, the layer of photoresist is patterned and developed, calibration spheres are deposited on the layer of material, the exposed portions of the layer of material is etched leaving structures having the shape of the developed layer of photoresist and pillars under the calibration spheres. The calibration spheres are then removed and the wafer is run through a scan tool to determine the sensitivity of the scan tool.
The described invention thus provides a method of manufacturing calibration wafers that allow an accurate determination of the sensitivity of scan tools.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described embodiments of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
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patent: 5757474 (1998-05-01), Sopori
patent: 5767967 (1998-06-01), Yufa
patent: 6034769 (2000-03-01), Yufa
patent: 6173604 (2001-01-01), Xiang
patent: 6185472 (2001-02-01), Onga
patent: 6208156 (2001-03-01), Hembree
Advanced Micro Devices , Inc.
Nelson H. Donald
Niebling John F.
Stevenson Andre′n C.
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