Method of manufacturing bipolar transistor

Fishing – trapping – and vermin destroying

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437 33, 437162, 437197, 437233, 437191, H01L 21306

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048309729

ABSTRACT:
A method of manufacturing an ultra-miniaturized bipolar transistor is disclosed, wherein an insulating film and a first polysilicon film doped with an impurity of a second conductivity type are formed, in this order, as a collector on a semiconductor layer of a first conductivity type. After an opening is formed in a predetermined portion of the first polysilicon film, the insulating film is etched, using the first polysilicon film as a mask, to expose part of a surface of the substrate. Thereafter, an undoped second polysilicon film is deposited on the resultant structure, and is annealed without etching. Then, the impurity doped in the first polysilicon film is diffused into part of the second polysilicon film and simultaneously into the substrate to form an external base region of a second conductivity type. The second polysilicon film is etched by use of an etching method wherein the etching rate in an undoped region is much higher than that in an impurity-doped region. As a result, the undoped region can be selectively removed without using a mask, thereby exposing the substrate surface. Subsequently, an oxide film is formed on the polysilicon film and the substrate surface, and an impurity is doped through the opening to form an internal base layer. Thereafter, an emitter layer is formed, in a self-aligned manner, in the internal base region.

REFERENCES:
patent: 4463493 (1984-08-01), Momose
patent: 4531282 (1985-07-01), Sakai
patent: 4571817 (1986-02-01), Birrittella
patent: 4717689 (1988-01-01), Maas
patent: 4746629 (1988-03-01), Hanagasaki
patent: 4780427 (1988-10-01), Sakai
Electronics Letters, vol. 19, No. 8, pp. 283-284, 1983 T. Sakai et al.
Denshitsushingakkaishi vol. J. 69-c, No. 2 pp. 176-181, 1986.

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