Method of manufacturing an intergrated circuit including steps f

Details Method of manufacturing an intergrated circuit including steps f Method of manufacturing an intergrated circuit including steps f

1989-12-04

1991-04-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437235, 156643, 156653, 156657, 148DIG43, H01L 21312, H01L 2147

Patent

active

050064851

ABSTRACT:
A method of manufacturing integrated circuit is set forth in which a plurality of conducting patterns are formed on a substrate and dielectric material is deposited on the surface of the substrate and thereafter etched. The invention involves forming the dielectric material from two separate dielectric layers having respectively formed thicknesses such that upon etching the top dielectric layer is completely removed, while the underlying dielectric layer is removed according to the underlying type of conductive pattern.

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patent: 4692204 (1987-09-01), Fabien et al.
patent: 4839311 (1989-06-01), Riley et al.
Soderman, "Polysilicon Gate FET Process with Substrate Contacts", IBM Tech. Disc. Bul., vol. 21, No. 3, 8/78.

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