Method of manufacturing an integrated semiconductor circuit incl

Details Method of manufacturing an integrated semiconductor circuit incl Method of manufacturing an integrated semiconductor circuit incl

1990-09-14

1991-12-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 33, 437133, 437909, 437 60, 148DIG11, 148DIG72, H01L 21265

Patent

active

050735080

ABSTRACT:
The invention relates to a method of manufacturing a non-planar HBT transistor comprising first the step of forming the emitter, the step of etching the device around the emitter as far as the level of the base layer, exposing a region for the collector contact, the emitter being protected, and then the step of forming the base contact by self-alignment on the emitter and the collector. This method utilizes steps of profile inversion, during which two dielectric layers of different materials are successively deposited, the first of which has a uniform thickness and the second of which has a non-uniform thickness and which are etched at different rates in order to cause chosen patterns to appear. The invention moreover permits forming concomitantly buried resistors. The device obtained is particularly compact and performant and the method requires only a very limited number of masking steps, which can be realized with a non-critical resolution.

REFERENCES:
patent: 4617724 (1986-10-01), Yokoyama et al.
patent: 4889831 (1989-12-01), Ishii et al.

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