METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT, INTEGRATED...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S765010, C324S1540PB

Reexamination Certificate

active

06930499

ABSTRACT:
The invention relates to a method of manufacturing an integrated circuit (404) on a die (402), wherein the die (402) forms a detachable part of a wafer (401) comprising a plurality of dies that are separated from each other by dicing lanes (403). The method comprises a step of applying a metallization pattern (407) in at least one of the dicing lanes (403) to form a communication bus comprising at least one communication bus circuit (405) that is part of the integrated circuit (404). Said step is followed by a step wherein the integrated circuit (404) is tested according to a predetermined testing method which uses the communication bus circuit (405) to communicate with the integrated circuit (404). This step is followed by a next step wherein the die (402) is detached from the wafer (401). The communication bus circuit (405) is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (404), it communicates in the wafer test mode. The invention also relates to an integrated circuit (404) obtained by means of the manufacturing method, a wafer (401) comprising an integrated circuit (404) obtained by means of the manufacturing method, and a system comprising an integrated circuit (404) obtained by means of the manufacturing method.

REFERENCES:
patent: 3849872 (1974-11-01), Hubacher
patent: 5053700 (1991-10-01), Parrish
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5442282 (1995-08-01), Rostoker et al.
patent: 5446395 (1995-08-01), Goto
patent: 5557573 (1996-09-01), McClure
patent: 5808947 (1998-09-01), McClure

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