Method of manufacturing an integrated circuit including planariz

Details Method of manufacturing an integrated circuit including planariz Method of manufacturing an integrated circuit including planariz

1992-03-16

1994-11-22

Thomas, Tom

Fishing, trapping, and vermin destroying

437225, 437235, 437974, 148DIG12, 156645, H01L 21302

Patent

active

053669240

ABSTRACT:
A process for planarizing a bonded wafer. The wafer has a layer of exposed oxide thereon which acts as a reference for the grinding and polishing of the wafer. The resulting ground and polished wafer has a thinned, substantially planar, working layer for subsequent fabrication of transistors, etc.

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"A Bonded-SOI-Wafer CMOS 16-Bit 50 KSPS Delta-Sigma ADC", IEEE 1991 Custom Integrated Circuits Conference, Takaramoto, Harajiri, Sawada, Kobayashi, Gotoh, pp. 18.1.1 through 18.1.4.

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