Method of manufacturing an insulated gate field effect transisto

Metal working – Method of mechanical manufacture – Assembling or joining

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29578, 29577C, 29590, 29576W, 29576B, 148 15, H01L 2126

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active

046163999

ABSTRACT:
A method of manufacturing an insulated gate field effect transistor has first and second impurity doping processes for forming source and drain regions. In the first doping process, an impurity is lightly doped in the source and drain forming regions in self-alignment with a silicon gate pattern and a field insulating film. Next, a heat treatment is conducted so that the side surface portions of the silicon gate pattern are converted into silicon oxide films having a predetermined thickness. Thereafter, the second doping process is conducted in which an impurity is heavily doped in each part of the source and drain forming region in self-alignment with the silicon oxide films and the field insulating film. Each of source and drain region manufactured by the method has a first part of low impurity concentration adjacent to a channel region and a second part of high impurity concentration positioned between the first part and the field insulating film. The deviation of the thickness of the silicon oxide film is very small, and the length of the first part depends on that thickness. On the other hand, the length of the first part of source, drain region influences the performance of the transistor, and therefore, the method can manufacture the transistor of a stable quality.

REFERENCES:
patent: 4356623 (1982-11-01), Hunter
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4404733 (1983-09-01), Sasaki
patent: 4419809 (1983-12-01), Riseman et al.
patent: 4441247 (1984-04-01), Gargini et al.
patent: 4503601 (1985-03-01), Chiao
IEEE Transaction on Electron Devices, vol. Ed. 27, No. 8, 8/80, Design & Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor, by: Seiki Ogura, et al.
IEEE Transactions on Electron Devices, vol. Ed. 29, No. 4, 4/82, Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology, By: Seike Ogura, et al.

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