Method of manufacturing an insulated gate field effect transisto

Details Method of manufacturing an insulated gate field effect transisto Method of manufacturing an insulated gate field effect transisto

1990-05-08

1992-02-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 67, 437153, 437164, 437203, 148DIG126, H01L 21225, H01L 21336

Patent

active

050860070

ABSTRACT:
Improved insulated gate field effect transistors and methods of manufacture are disclosed wherein a self aligned source region is formed in the sides of a groove or indentation in a semiconductor substrate. By eliminating photolithography steps, yield is improved and manufacturing cost is reduced while achieving fine tolerances. As a result, reduction in cell size of approximately a factor of 6 is possible and channel resistance is reduced, allowing for increased current capacity. Source regions (26) are formed by dopant outdiffusion from insulating portions (24C).

REFERENCES:
patent: 3685140 (1972-08-01), Engeler
patent: 4370180 (1983-01-01), Azuma et al.
patent: 4520552 (1985-06-01), Arnould et al.
patent: 4853345 (1989-08-01), Himelick
Ueda, D., et al., "An Ultra-Low Oh-Resistance . . . " IEEE Trans. Electron Devices, vol. ED-34, No. 4, Apr. 1987, pp. 926-930.

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