Method of manufacturing an insulated gate FET having double-laye

Details Method of manufacturing an insulated gate FET having double-laye Method of manufacturing an insulated gate FET having double-laye

1994-04-20

1995-05-30

Hearn, Brian

Fishing, trapping, and vermin destroying

437 27, 437 34, 437 40, 437913, H01L 2170

Patent

active

054200628

ABSTRACT:
This invention relates to an insulated gate FET in which the withstanding voltage and the latch-up resistant property are both made high. The structure thereof includes a second well formed in a first well and having an impurity concentration lower than that of the first well. Source and drain electrodes of the FET are formed in the second well.

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