Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2006-05-30
2006-05-30
Smith, Matthew (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C257SE21001, C257SE21499
Reexamination Certificate
active
07052933
ABSTRACT:
The invention relates to a method of manufacturing a semiconductor device (10), whereby an electric element (11) is attached on or above a carrier plate (4) which comprises a first layer (5) of a first material and a second layer (2) of a second material which differs from the first, which is electrically conducting, which has a smaller thickness than the first layer (5), and in which a cavity (6) is formed that extends at least to the first layer (5). The element (11) is electrically connected to parts (2) of the carrier plate (4) at first connection regions (1), and an encapsulation is deposited around the element (11) and in the cavity (6). Then so much of the first layer (5) of the carrier plate (4) is removed that the cavity (6) is reached, whereby second connection conductors (2) are formed from the remaining portion of the carrier plate (4).According to the invention, at least one further cavity (7) is formed in a portion of the carrier plate (4) surrounded by the cavity (6) before the encapsulation (3) is deposited, which further cavity (7) becomes at least substantially filled with a portion of the encapsulation (3) during the deposition thereof and, within the second connection regions (2), separates a portion (2A) thereof from the remaining portion (2B) thereof, the smallest dimension of the portion (2A) being chosen to be smaller than the smallest dimension of the remaining portion (2B) of each second connection region (2). The portion (2A) may thus be readily provided with solder (8A) having a smaller thickness than the solder (8B) in the remaining portion of the second connection region (2). This is an advantage, for example in the case of surface mounting of the device (10). Preferably, the first connection regions (1) are connected to the portion (2A) of the connection region (2).
REFERENCES:
patent: 5814894 (1998-09-01), Igarashi et al.
patent: 6963126 (2005-11-01), Sakamoto et al.
patent: 1 143 509 (2001-10-01), None
patent: 1 187 205 (2003-03-01), None
Van Veen Nicolaas Johannes Anthonius
Weekamp Johannus Wilhelmus
Koninklijke Philips Electronics , N.V.
Smith Matthew
Toledo Fernando L.
Zawilski Peter
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