Method of manufacturing an electrode substrate resistant to...

Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal

Reexamination Certificate

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C349S046000, C349S051000, C349S149000

Reexamination Certificate

active

06411350

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrode substrate including a base substrate and electrode wires formed thereon, for example, an array substrate for a display device for use in a liquid crystal display device and a method for manufacturing the same.
2. Description of the Related Art
In recent years, flat panel display devices, represented by a liquid crystal display device, are used in various fields, such as television display devices, computer display devices and display devices for use in car navigation systems, utilizing the characteristics that it is light weight, thin package size, and low power consumption, as compared to display devices such as CRTs.
In particular, active matrix display devices have been researched and developed, since an image can be displayed satisfactorily without cross talk between adjacent pixels. In an active matrix display device, switch elements, such as thin-film-transistors (TFTs) or metal-insulator-metals (MIMs), are respectively provided for display pixels.
Conventional art will be briefly described below, taking, for example, an active matrix liquid crystal display device in which TFTs are used as switch elements of the respective display pixels.
The active matrix liquid crystal display device comprises an array substrate including a plurality of pixel electrodes arranged in a matrix, and a liquid crystal composition, as an optical modulating layer, sealed between the array substrate and a counter substrate on which a counter electrode is formed. The array substrate has a transparent insulating substrate, e.g., a glass substrate, a plurality of TFTs arranged on the substrate, and a plurality of pixel electrodes connected to the TFTs. The array substrate also includes 480 scanning lines connected to the gate electrodes of the TFTs arranged in a row direction, 640×3 signal lines connected to the drain electrodes of the TFTs arranged in a column direction, and 480 storage capacitor lines arranged opposite to the pixel electrodes via an insulating layer so as to form storage capacitors C
s
.
Recently, as regards the liquid crystal display devices, such as the flat panel display device, there is a demand for a high resolution display image of a large size display region having a diagonal line of, for example, 10 inches or greater. To meet the demand, an array substrate for such a large refined display device is required. However, the array substrate is so large that the overall substrate cannot be exposed at a time in an exposing step in the array substrate manufacturing steps, since the size of the exposure apparatus is restricted. Therefore, it is necessary to expose the overall exposure region of one array substrate in a plurality of segment regions, for example, four regions A
1
to A
4
as shown in FIG.
1
.
The four regions shown in
FIG. 1A
are: a first region Al exposed in a first exposing step; a second region A
2
exposed in a second exposing step; a third region A
3
exposed in a third exposing step; and a fourth region A
4
exposed in a fourth exposing step. A double exposure region A
1
+A
2
, which is exposed twice, is formed between the first region A
1
and the second region A
2
. The double exposure region is formed, so that an unexposed portion may not be formed between the exposure regions. Similarly, double exposure regions A
1
+A
3
, A
3
+A
4
and A
2
+A
4
are formed respectively between the regions A
1
and A
3
, between the regions A
3
and A
4
, and between the regions A
2
and A
4
.
Each of the double exposure regions A
1
+A
2
, A
1
+A
3
, A
3
+A
4
and A
2
+A
4
are exposed with at least two masks in the aforementioned segment exposure method. Therefore, in the double exposure region, a wiring defect, such as breakage, is liable to occur in the wire pattern in a higher possibility as compared to the other regions.
For example, to form an electrode wire on a glass substrate, an aluminum thin film is deposited on the glass substrate and then patterned into an electrode wire. In this patterning, photoresist is first applied to the aluminum thin film, and after the photoresist is dried, it is selectively exposed using a mask defining a predetermined wire pattern. In the segment exposure method, a plurality of masks are prepared, which have characteristic patterns corresponding to the wires to be formed in the respective exposure regions.
FIG. 1B
shows a first exposure image RP
1
exposed by the first exposing step for forming an electrode wire and a second exposure image RP
2
exposed by the second exposing step. The first and second exposure images RP
1
and RP
2
in
FIG. 1B
respectively correspond to regions masked by the masks for defining the wire patterns of the respective exposure regions. The photoresist in the regions exposed in the exposing steps is removed by a developing process, thereby exposing a portion of the aluminum thin film. Thereafter, the exposed portion of the aluminum film is removed by an etching process, with the result that only that portion of the aluminum pattern, which corresponds to the wire patterns, remains. Then, the photoresist is removed, thereby forming an electrode wire.
In this case, due to mask alignment accuracy, distortion of the substrate or a difference in accuracy between the masks, a wire width W
1
of the first exposure image RP
1
and a wire width W
2
of the second exposure image RP
2
may be different from each other, as shown in
FIG. 1B
, or the exposure images may be deviated from each other. Accordingly, as shown in
FIG. 1C
, a wire width W
1
0
of an electrode wire patterned on the basis of the first exposure image RP
1
is different from a wire width W
2
0
of an electrode wire patterned on the basis of the second exposure image RP
2
.
Further, the double exposure region A
1
+A
2
exposed in the first and second exposing steps is patterned on the basis of the first and second exposure regions A
1
and A
2
. Therefore, as shown in
FIG. 1C
, a wire width W
3
of an electrode wire may be very small, or a wire defect may be caused due to mask alignment accuracy, distortion of the substrate or a difference in accuracy between the masks. Such a problem may also arise in the other double exposure regions.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an electrode substrate having a structure which does not easily arise a defect, such as a wire breakage, and also a method for manufacturing the electrode substrate. Another object of the present invention is to provide a display device which assures a high manufacturing yield.
According to an aspect of the present invention, there is provided an electrode substrate comprising:
a first conductive layer having a first wire pattern made of a first conductive member, and a second wire pattern made of the same member as the first wire pattern, the first and second wire patterns being formed on one plane; and
a second conductive layer having a third wire pattern made of a second conductive member deposited on part of the first wire pattern, and a fourth wire pattern deposited on another part of the first wire pattern on which the third wire pattern is not formed, the second wire pattern, and a boundary region between the first and second wire patterns, the third and fourth wire patterns being formed of the same member.
According to another aspect of the present invention, there is provided an electrode substrate for use in a display device, comprising:
an insulating member having at least one substantially flat surface;
a plurality of pixel electrodes arranged in a matrix on the substantially flat surface of the insulating member;
a first conductive layer, formed on the substantially flat surface of the insulating member, and having a first wire pattern made of a first conductive member, and a second wire pattern made of the same member as the first wire pattern, the first and second wire patterns being formed on one plane; and
a second conductive layer having a third wire pattern made of a

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