Method of manufacturing an EEPROM having an erasing gate electro

Details Method of manufacturing an EEPROM having an erasing gate electro Method of manufacturing an EEPROM having an erasing gate electro

1991-07-08

1994-11-15

Fourson, George

Fishing, trapping, and vermin destroying

437 48, 437 49, 437941, H01L 21265

Patent

active

053648056

ABSTRACT:
A memory cell array is formed of a plurality of nonvolatile memory cell transistors arranged in a matrix form. The patterns of the control gate electrode and the source region of each memory cell transistor are formed in parallel and the pattern of the erasing gate electrode is formed to intersect the source region and control gate electrode patterns. A field oxide film is formed in an intersecting portion between the source region and the erasing gate electrode.

REFERENCES:
patent: 4257826 (1981-03-01), Matalone, Jr.
patent: 4258466 (1981-03-01), Kuo et al.
patent: 4466081 (1984-08-01), Masuoka
patent: 4851364 (1989-07-01), Yatsuda et al.
patent: 4910565 (1990-03-01), Masuoka
patent: 4924437 (1990-05-01), Paterson et al.
patent: 4967393 (1990-11-01), Yokoyama et al.

Affiliated with

Also associated with

Rating

Method of manufacturing an EEPROM having an erasing gate electro does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing an EEPROM having an erasing gate electro, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing an EEPROM having an erasing gate electro will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1097376