Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
2002-05-30
2003-09-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S154000, C438S587000, C438S153000, C438S149000, C438S029000
Reexamination Certificate
active
06627471
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2001-30702, filed on Jun. 1, 2001 in Korea, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an array substrate of a liquid crystal display (LCD) device and more particularly, to a method of manufacturing an array substrate having drive integrated circuits (drive ICs).
2. Discussion of the Related Art
Due to a rapid development in information technology, display devices have evolved into instruments that can process and display a great deal of information. Flat panel display devices, which have properties of being thin, low weight and low power consumption, such as liquid crystal display (LCD) devices, have been developed. The LCD device is widely used for notebook computers and desktop monitors, etc. because of its superior resolution, color image display and quality of displayed images. The LCD device consists of an upper substrate, a lower substrate and a liquid crystal layer disposed between the upper and lower substrates. The LCD device uses an optical anisotropy of liquid crystal and produces an image by controlling light transmissivity by varying the arrangement of liquid crystal molecules, which are arranged by an electric field.
One substrate of the LCD device includes a thin film transistor that acts as a switching device. An LCD device, which includes the thin film transistor, is referred to as an active matrix liquid crystal display (AMLCD) and it has a high resolution and can display an excellent moving image. Amorphous silicon is widely used as an active layer of the thin film transistor because amorphous silicon can be formed on a large, low cost substrate such as glass.
The LCD device also includes a drive integrated circuit (drive IC) that controls the thin film transistor. Unfortunately, amorphous silicon does not form a suitable active layer for the drive IC, which usually includes CMOS (complementary metal-oxide-semiconductor) devices that require crystalline silicon as active layers. Because of this, the drive IC is usually connected to the array substrate using a TAB (tape automated bonding) system. This adds significant cost to the LCD device.
Because of limitations of amorphous silicon, an LCD device that incorporates polycrystalline silicon as an active layer is being researched and developed. Polycrystalline silicon is highly beneficial because it is much better suited for use in the drive IC than amorphous silicon. Polycrystalline silicon thus has the advantage that the number of fabrication steps could be reduced because a thin film transistor and a drive IC could be formed on the same substrate, eliminating the need for TAB bonding. Furthermore, the field effect mobility of polycrystalline silicon is 100 to 200 times greater than that of amorphous silicon. Polycrystalline silicon is also optically and thermally stable.
FIG. 1
is a schematic block diagram showing an array substrate of a conventional liquid crystal display (LCD) device having drive integrated circuits (drive ICs). In
FIG. 1
, the LCD device includes a driving portion
3
and an image portion
4
on a substrate
2
. The image portion
4
is located in the center of the substrate
2
, and the gate driving portion
3
a
and the data driving portion
3
b
are located in the left and top regions of the substrate
2
. In the image portion
4
, a plurality of gate lines
6
are disposed horizontally and a plurality of data lines
8
are disposed vertically. The gate lines
6
and the data lines
8
cross each other to define a plurality of pixel regions. A pixel electrode
10
is disposed in the pixel region and a thin film transistor “T”, switching device, is formed in the form of matrix at each crossing of the gate lines
6
and the data lines
8
. Each thin film transistor “T” is connected to each pixel electrode
10
. The gate driving portion
3
a
, which includes a plurality of drive ICs, supplies an address signal to the gate lines
6
, and the data driving portion
3
b
, which also includes a plurality of drive ICs, supplies an image signal to the data lines.
The gate driving portion
3
a
and the data driving portion
3
b
are electrically connected to an outer control circuit (not shown) with signal input terminals
12
which are formed on one edge of the substrate
2
, so that the outer control circuit (not shown) controls the drive ICs of the gate driving portion
3
a
and the data driving portion
3
b
. The outer control circuit (not shown) applies signals to the gate and data driving portions
3
a
and
3
b
through the signal input terminals
12
.
As stated above, the gate driving portion
3
a
and the data driving portion
3
b
includes drive ICs having a CMOS (complementary metal-oxide-semiconductor) transistor as an inverter which changes a direct current into an alternating current. The CMOS transistor comprises an n-channel MOS transistor, in which electrons are the majority carriers, and a p-channel MOS transistor, in which holes are the majority carriers. Therefore, in n-channel MOS transistor, most of the current is carried by negatively charged electrons and in p-channel MOS transistor, most of the conduction is carried by positively charged holes.
The thin film transistor “T” of the image portion
4
and CMOS transistor (not shown) of the driving portion
3
use polycrystalline silicon as an active layer, and thus can be formed on the same substrate
2
.
FIGS. 2A and 2B
are cross-sectional views showing conventional thin film transistors posited in an image portion and in a driving portion, respectively. The thin film transistors have a top-gate type structure in which a gate electrode is formed on a semiconductor film.
In
FIG. 2A
, i.e., in the image portion, a buffer layer
14
is formed on a transparent substrate
1
. A semiconductor layer
16
is formed on the buffer layer
14
, and the semiconductor layer
16
consists of four portions, i.e., an active layer
16
a
in the middle of the semiconductor layer
16
, source and drain regions
16
c
and
16
d
in both ends of the semiconductor layer
16
, and lightly doped drain (LDD) region
16
b
disposed between the active layer
16
a
and the source region
16
c
or the active layer
16
a
and the drain region
16
d
. The LDD region
16
b
includes impurities of low density and prevents leakage current of an off-state, that is, applying reverse bias to thin film transistor. A gate insulator
18
is formed on the active layer
16
a
and a gate electrode
20
is formed on the gate insulator
18
. An inter layer insulator
24
is formed the gate electrode
20
and covers the gate electrode
20
. The inter layer insulator
24
has first and second contact holes
22
a
and
22
b
exposing the source and drain regions
16
c
and
16
d
, respectively. Next, source and drain electrodes
26
and
28
are formed on the inter layer insulator
24
, and the source and drain electrodes
26
and
28
are connected to the source and drain regions
16
c
and
16
d
through the first and second contact holes
22
a
and
22
b
, respectively. A passivation layer
32
is formed on the source and drain electrodes
26
and
28
, and covers the source and drain electrodes
26
and
28
. The passivation layer
32
has third contact hole
30
exposing the drain electrode
28
. A pixel electrode
34
is formed on the passivation layer
32
and the pixel electrode
34
contacts the drain electrode
28
through the third contact hole
30
of the passivation layer
32
.
The source and drain regions
16
c
and
16
d
of
FIG. 2A
include donor impurities from group V of the periodic table and most of current is carried by electrons. Accordingly, the thin film transistor “A” of
FIG. 2A
is n-channel MOS transistor.
As shown in
FIG. 2B
, CMOS transistor in the driving portion comprises n-channel MOS transistor “B” and p-channel MOS transistor “C”. In
FIG. 2B
, a buffer layer
14
is formed on a transparent substrate
1
. Next, semiconductor layers
Anya Igwe U.
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
Smith Matthew
LandOfFree
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