Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-07-24
2002-10-29
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S640000, C257S760000
Reexamination Certificate
active
06472719
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention.
The invention relates to the fabrication of Integrated Circuit devices and more specifically to the formation of air gaps as a low dielectric constant material between conductor lines on the same or on different levels.
(2) Description of the Prior Art.
The formation of air gaps between conducting lines of high speed Integrated Circuits (IC's) is typically a combination of the deposition of a metal layer, selective etching of the metal layer to form the desired line patterns, the deposition of a porous dielectric layer or a disposable liquid layer which is then selectively removed to form the desired air-gaps.
The continuing effort to reduce the size of individual transistors and other devices commonly integrated on a semiconductor chip and to increase the density of Integrated Circuits results in a continuing reduction of the separation between conducting layers of materials. This reduction results in an increase of capacitive crosstalk between adjacent conductor lines of a semiconductor circuit, that is the voltage on the first conductor line alters or affects the voltage on the second conductor line. This alteration in voltage can cause erroneous voltage levels in the Integrated Circuit making the IC increasingly prone to faulty operation. It becomes therefore imperative to reduce the resistive capacitance (RC) time constant and the crosstalk between adjacent conducting lines.
The capacitance between adjacent conducting lines is highly dependent on the insulator or dielectric used to separate the conducting lines. Semiconductor fabrication typically uses silicon dioxide as a dielectric; this has a dielectric constant of about 3.9.
The use of many of the low dielectric constant materials is not feasible due to the fact that equipment is not available to properly process the new dielectric material in various integrated circuits. Also, the chemical or physical properties of many low dielectric constant materials are usually difficult to make compatible with or integrate into integrated circuit processing.
The lowest possible and therefore the ideal dielectric constant is 1.0, this is the dielectric constant of a vacuum whereas air has a dielectric constant of less that 1.001.
To reduce said capacitive coupling and reduce the capacitive crosstalk, a major objective in the design of IC's is to reduce the Dielectric Constant (k) of the insulating layer between adjacent conductor lines of semiconductor circuits. The present invention makes a significant contribution within the scope of this effort.
U.S. Pat. No. 5,324,683(Fitch et al.) shows a method for forming an air gap between metal lines by forming a dielectric layer between metal lines, forming an etch barrier layer(s) thereover and opening a hole in the etch barrier layer and isotropically etching the dielectric layer to form air gaps. This is close to the invention. However, the exact structures/steps differ.
U.S. Pat. No. 5,461,003(Havemann et al.) teaches air gap process by forming a porous layer over an oxide layer; and isotropically etching the oxide layer between the metal lines to form air gaps.
U.S. Pat. No. 5,641,712(Grivna et al.) shows a process to form air gaps between line by growing oxide.
U.S. Pat. No. 5,407,860(Stoltz et al.) disclose an air gap process by etching low-k material out between lines and forming a dielectric layer thereover.
U.S. Pat. No. 5,444,015(Aitken et al.) shows a method for forming air gap between metal lines by removing the dielectric material between the lines.
SUMMARY OF THE INVENTION
The principle object of the present invention is to provide and effective and manufacturable method of forming air gaps between conductive layers of material.
Another objective of the present invention is a method of reducing the dielectric constant k between conductive layers of material.
Another objective of the present invention is a method of reducing capacitive coupling between conducting layers of material.
Another objective of the present invention is a method of reducing capacitive crosstalk between conductive layers of material.
Another objective of the present invention is to reduce the potential for false or incorrect logic levels of the circuits in the IC's.
Another objective of the present invention is a method of reducing Resistive Capacitive delays of the circuits in the IC's.
Another objective of the present invention is to increase Switching Speed of the circuits in the IC's.
Another objective of the present invention is to provide a method for simplification of the semiconductor planarization process by means of the elimination of dummy blocks within the construct of the semiconductor circuits.
In accordance with the objects of the present invention a new method of forming air gaps between adjacent conducting lines of a semiconductor circuit is achieved.
The first embodiment of the present invention addresses, in accordance with the above stated objectives, a method for manufacturing air gaps in multilevel interconnections, comprising the steps of forming metal leads on top of an insulating layer, performing a Chemical Vapor Deposition (CVD) of oxide over the metal leads, performing a CVD of nitride over the layer of oxide, open a trench through the deposited nitride and into the deposited oxide down to a level not reaching the insulating layer, etch the trench down to the level of the insulating layer at the same time widening the trench, deposit a low step coverage of a dielectric layer on top of the nitride such that the dielectric does not penetrate the trench, perform Chemical Mechanical Planarization of the deposited dielectric down through the top layer of the deposited nitride, etch to remove the remaining nitride and deposit a low step coverage of dielectric material to enclose the air gap formed within the trench and the areas of the removed nitride.
The second embodiment of the present invention addresses, in accordance with the above stated objectives, a method for manufacturing air gaps in multilevel interconnections that encompasses the steps as indicated above within the first embodiment of the present invention but where the process of creating air gaps does not extend the step of CMP of the deposited dielectric down through the top layer of the deposited nitride. Under the second embodiment of the present invention, the air gap will be formed between the metal leads.
The third embodiment of the present invention comprises the steps of forming metal leads on top of an insulating layer, performing a Plasma Enhanced Chemical Vapor Deposition (PECVD) of oxide over the metal leads, performing a CVD of SOG over the layer of oxide, planarize the deposited layer of SOG down to below the top surface of the deposited PECVD oxide, deposit a thin layer of PECVD oxide over the planarized surface of the layer of SOG, open holes through the deposited PECVD oxide, etch the deposited SOG by vapor HF through the holes in the PECVD oxide down to the level of the insulating layer at the same time widening the openings in the SOG, remove the photoresist and deposit a low step coverage of a dielectric layer on top of the PECVD oxide such that the dielectric does not penetrate the openings in the PECVD oxide, perform curing of the deposited dielectric on top of the PECVD.
REFERENCES:
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5407860 (1995-04-01), Stoltz et al.
patent: 5444015 (1995-08-01), Aitken et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5641711 (1997-06-01), Cho
patent: 5641712 (1997-06-01), Grivna et al.
patent: 5843836 (1998-12-01), Cheung et al.
patent: 6197680 (2001-03-01), Lin et al.
patent: 6211057 (2001-04-01), Lin et al.
Chang Juin-Jie
Chen Yen-Ming
Huang Kuei-Wu
Lin Shih-Chi
Ackermar Stephen B.
Quach T. N.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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