Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
2002-08-06
2004-08-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S039000, C438S042000
Reexamination Certificate
active
06773945
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an under electrode structure used in an optical functional device using a semiconductor and an optical waveguide device, and a manufacturing method thereof.
There has recently been a demand for improvements in the performance of optical devices using semiconductor materials, such as a semiconductor laser, a PD, an optical modulator, an optical amplifier, etc. and reductions in the costs thereof.
Frequency response rated as giga hertz or more in particular has been required to achieve the improvements in performance. Attention has been paid to a ridge type optical waveguide as an optical waveguide structure to meet such a request.
The ridge type optical waveguide is characterized in that control on the width of a mesa stripe is easy in terms of its manufacture, and a structure is provided wherein a solid material having an electrical insulating property and used as a low permittivity material, i.e., an inorganic insulating material such as SiO
2
, SiN, SiON or the like, or an organic insulating material such as polyimide or the like, or a combination of these inorganic insulating material and organic insulating material is embedded in the sides of the mesa stripe in terms of its structure.
Voltage or current applying means is implemented by, for example, wire-bonding a metal film (rectangle represented in several tens of microns to a few hundred of microns) electrically connected from an upper end of the mesa stripe as viewed from a power feed line. The metal film will hereinafter be called an electrode pad. The ridge type optical waveguide is structurally characterized in that simply forming an organic insulating material such as polyimide or the like thick as an underbed or base for the electrode pad makes it possible to reduce electric capacity (hereinafter called electrode-to-electrode capacitance) between an electrode and GND.
The structure of the ridge type optical waveguide has been described in a typical reference, Yukio Noda, et al., “high-speed electroabsorption modulator stripe-loaded GaInAsP Planer waveguide” IEEE Journal of Lightwave Technology vol. LT-4, No. 10, 1986.
An electrode pad is electrically connected from an upper end of a mesa stripe that functions as an optical waveguide. Further, channel-shaped trenches provided at both ends of the mesa stripe and the lower side of the electrode pad are filled with polyimide having a thickness of about 1 &mgr;. Incidentally, while a layer structure of a semiconductor similar to the mesa stripe is provided outside the trenches as viewed from the mesa stripe, it provides a structure extremely effective in averaging the whole wafer so as to avoid the concentration of a stress on the mesa stripe in a process step or an assembly process, improving process reproducibility, etc. This structure will hereinafter be called a double channel ridge structure (abbreviated as a DC ridge structure). Incidentally, the mesa stripe and the trench lying under the electrode pad are collectively formed in the same process step (removed by etching). While an etching solution such as a hydrochloric acid etchant, an acetic acid etchant or the like is normally used, this is used to selectively etch only InP. Ternary and quaternary compositional layers such as InGaAs or InGaAsP, etc. can be used as etching masks. Namely, an ohmic contact layer corresponding to the top semiconductor layer of the mesa stripe functions as an etching mask, and an optical waveguide functions as an etching stopper layer. Further, the progress of etching in horizontal and vertical directions can automatically be controlled. This results in the feature of a method of manufacturing the ridge type optical waveguide.
Incidentally, the DC ridge type structure has been disclosed even in Japanese Patent Application Laid-Open Nos. 11(1999)-202274 and 07(1995)-230067 and Japanese Patent Application Laid-Open No. Hei 2001-091913.
The conventional structure presents the following problems. Upon etching the p-InP layer, the etching proceeds fast at each projecting comer where the etching layer lying under the electrode and each of the channels on the sides of the mesa stripe join. This results from the fact that the mask does not function as the mask upon etching at the protruding comer. Finally, the etching obliquely proceeds at its point alone. As a result, a p
+
-InGaAs contact layer used as a mask protrudes.
Thus the conventional structure shows problems about a structural defect, instability of a manufacturing process, etc., such as the following problems:
(a) While the p-InP clad layer is obliquely etched, the angle thereof and the amount of etching thereof are unstable.
(b) The polyimide is hard to enter under the protruding p
+
-InGaAs (P) contact layer and hence a cavity or void might be defined.
(c) In a subsequent wafer process step, the protruding p-InGaAs(P) contact layer might be chipped.
These problems lead to yield degradation, long-term reliability degradation, and characteristic degradation.
SUMMARY OF THE INVENTION
With the foregoing problems in view, the present invention may provide an under electrode structure and a manufacturing method thereof capable of avoiding instability of an etching angle and the amount of etching.
A method of manufacturing a waveguide optical semiconductor device according to the present invention comprises providing a semiconductor substrate including a lower clad layer, a core layer, an upper clad layer and a contact layer formed on the substrate in that order. Next, the contact layer and a part of the upper clad layer is removed by a dry etching method within a pair of line patterns located in parallel and an independent rectangular pattern located near the line patterns. Then, the remaining upper clad layer is removed by a wet etching method so as to expose the core layer within the line patterns and the independent rectangular pattern. An insulating material is coated on the exposed core layer. Then the insulating material formed on the contact layer is removed within a region located between the pair of line patterns so that a part of the contact layer is exposed. An electrode layer is formed on the exposed contact layer. Finally, a bonding pad layer is formed over the independent rectangular pattern and a part of the electrode layer.
REFERENCES:
patent: 4788159 (1988-11-01), Smith
patent: 5723360 (1998-03-01), Iwasaki
patent: 5764842 (1998-06-01), Aoki et al.
patent: 5770474 (1998-06-01), Kim
patent: 5834329 (1998-11-01), Kim et al.
patent: 5880487 (1999-03-01), Furukawa et al.
patent: 6200826 (2001-03-01), Kim
patent: 6323530 (2001-11-01), Kubota
patent: 6374028 (2002-04-01), Yamada et al.
patent: 6459840 (2002-10-01), Sato et al.
patent: 07-230067 (1995-08-01), None
patent: 11-202274 (1999-07-01), None
patent: 2001-091913 (2001-04-01), None
Yukio Noda et al., “High-Speed Electroabsorption Modulator with Strip-Loaded GaInAsP Planar Waveguide,” Journal of Lightwave Technology, vol. LT-4, No. 10, Oct. 1986, pp. 1445-1453.
Malsawma Lex H.
Oki Electric Industry Co. Ltd.
Smith Matthew
Volentine & Francos, PLLC
LandOfFree
Method of manufacturing a waveguide optical semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a waveguide optical semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a waveguide optical semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3305528