Fishing – trapping – and vermin destroying
Patent
1985-07-16
1987-08-04
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
357 234, 148DIG168, 437 40, 437225, H01L 21385, H01L 21388, H01L 2140, H01L 2978
Patent
active
046836438
ABSTRACT:
A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.
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patent: 4476622 (1984-10-01), Cogan
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"VMOS ROM" by T. J. Rodgers et al., IEEE Journal of Solid-State Circuits, vol. SC-11, No. 5, Oct. 1976, pp. 614-621.
"VMOS: High-Speed TTL Compatible MOS Logic" by T. J. Rodgers et al., IEEE Journal of Solid-State Circuits, vol. SC-9, No. 5, Oct. 1974.
Minegishi Kazushige
Miura Kenji
Morie Takashi
Nakajima Shigeru
Somatani Toshifumi
Chaudhuri Olik
Nippon Telegraph and Telephone Corporation
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