Etching a substrate: processes – Forming or treating electrical conductor article – Forming or treating of groove or through hole
Reexamination Certificate
2000-10-12
2003-09-30
Utech, Benjamin L. (Department: 1765)
Etching a substrate: processes
Forming or treating electrical conductor article
Forming or treating of groove or through hole
C216S017000, C216S041000, C216S079000, C216S013000, C438S720000, C438S723000, C438S687000
Reexamination Certificate
active
06627093
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to the manufacture of integrated circuits, more particularly the making of vertical metal connections (commonly referred to as “vias” by those skilled in the art) using a “damascene” type process, as it is called by those skilled in the art.
A damascene process may be carried out in a number of alternative ways, such as, in particular, the variant referred to as “single damascene”, or the variant referred to as “autoaligned dual damascene”, or the variant referred to as “inverse dual damascene”.
In the variant referred to as “single damascene”, the via is formed by making a cavity in the dielectric material deposited between two metallization levels of the integrated circuit, whereafter the cavity is filled with a metal.
In the variant referred to as “autoaligned dual damascene”, the cavities of the vias to be formed and the cavities of the future tracks of the upper metallization level are simultaneously etched. Next, all these cavities will be filled with a filling metal to form the vias and the tracks of the upper metallization levee In this variant, the inter-level dielectric material (that is, the dielectric material situated between two adjacent metallization levels) and the inter-track dielectric material situated at-the metallization level n+1 (that is, the dielectric material situated at the level n+1 between the tracks of this level) are separated by a stop layer, which is typically made of silicon nitride.
The variant referred to as “inverse dual damascene” differs from the “autoaligned dual damascene” variant in that in the former variant it is possible to omit the silicon nitride layer between the inter-level dielectric material and the inter-track dielectric material.
It proved to be very interesting to use copper for the metal tracks of one metallization level because copper has a better conductivity than, for example, aluminum. Meanwhile, the use of such a material is very tricky because there is a risk of diffusion of copper atoms into the dielectric materials, which might cause leakage currents between vias or between metal tracks. In addition, the copper may diffuse to the transistors and have an adverse effect on the functioning thereof.
The invention particularly relates to conductive materials, notably copper but also gold or alloys thereof, which diffuse or migrate into the dielectric materials and, more generally, into all materials used in microelectronics.
SUMMARY OF THE INVENTION
It is an object of the invention, in particular, to provide integrated circuits having metallization levels of copper, using a damascene-type process to make the vias of the integrated circuit, while precluding the diffusion of copper particles into the dielectric materials.
The invention applies to all types of damascene processes, more particularly to the variants mentioned hereinabove.
This object is achieved, in accordance with the invention, by a method of manufacturing a vertical metal connection which is supported by a portion of a metallization level of an integrated circuit.
Said portion being made of a conductive material (for example copper) and covered with an encapsulation layer, (e.g. of silicon nitride), said method includes, in accordance with a general characteristic of the invention, the deposition on said conductive portion thus covered of at least a layer of a dielectric material (typically ethyl tetraorthosilicate), whereafter the layer of dielectric material is etched so as to form a cavity at the location of the future vertical connection. The method further includes the deposition of at least one protective layer in said cavity to preclude diffusion of the conductive material, whereafter the protective layer at the bottom of the cavity is anisotropically etched, and the encapsulation layer is also etched, after which the cavity is filled with a conductive filler material, such as copper, aluminium, tungsten.
In practice, a single protective layer is used when a “single damascene” or “autoaligned dual damascene” type process is carried out. On the other hand, when in accordance with the invention, an “inverse dual damascene” type process is used, the process in accordance with the invention advantageously includes, after the protective layer and the encapsulation layer at the bottom of the cavity have been etched, the deposition of a second protective layer at the bottom and on the walls of the cavity. This enables direct contact between the copper (for example) and the dielectric material to be avoided at the level of the intermediate, horizontal plane of the cavity. Therefore, the possibility of depositing a second protective layer can be considered in all damascene processes where there is a risk of direct contact between the copper and the dielectric material.
The protective layer is advantageously composed of a material selected particularly from the group formed by tantalum, tantalum nitride, titanium and titanium nitride.
Thus, in accordance with the invention, the contaminating elements of copper, resulting from etching the encapsulation layer, are situated on the right side of the protective layer, i.e. they do not contact the dielectric material.
Thus, the method in accordance with the invention protects the oxide from contamination by copper and enables a cleaning step using chemical agents to eliminate the contaminating copper particles to be omitted.
Furthermore, the absence of the barrier layer at the bottom of the via enables a sizeable reduction of the resistance of the via when a single protective layer is deposited.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter by way of non-limitative example.
REFERENCES:
patent: 5741626 (1998-04-01), Jain et al.
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5818069 (1998-10-01), Kadosh et al.
patent: 6093627 (2000-07-01), Sung
patent: 6265313 (2001-07-01), Huang et al.
patent: WO 01/20665 (2001-03-01), None
Froment Benoit
Gayet Phillipe
Van Der Vegt Erik
Ahmed Shamim
Koninklijke Philips Electronics , N.V.
Utech Benjamin L.
Waxler Aaron
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