Method of manufacturing a vertical field effect transistor

Details Method of manufacturing a vertical field effect transistor Method of manufacturing a vertical field effect transistor

1992-07-08

1994-08-23

Quach, T. N.

Fishing, trapping, and vermin destroying

437 41, 437200, 437204, 437911, H01L 21335

Patent

active

053407571

ABSTRACT:
In the method of manufacturing a vertical field effect transistor, the gate region situated on either side of the source region projecting from a main face of a semiconductive substrate consists in implanting ions on either side of the source region to form a junction, and in forming a metal silicide on the gate region made in this way. Such a transistor is particularly suitable for being integrated in various MOS technologies, and in particular in CMOS.

REFERENCES:
patent: 4199771 (1980-04-01), Nishizawa et al.
patent: 4364072 (1982-12-01), Nishizawa
patent: 4403396 (1983-09-01), Stein
patent: 4449284 (1984-05-01), Shimbo
patent: 4497107 (1985-02-01), Cogan
patent: 4505022 (1985-03-01), Briere
patent: 4543706 (1985-10-01), Bencuya et al.
patent: 4713358 (1987-12-01), Bulat et al.
patent: 4766088 (1988-08-01), Kono et al.
patent: 4952990 (1990-08-01), Gruning
IBM Technical Disclosure Bulletin, vol. 25, No. 3A, Aug. 1982, New York, pp. 981-982, S. P. Gaur et al. "Vertical Jfet Integrated with Self-Aligned Bipolar Process".

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