Method of manufacturing a vertical channel FET

Details Method of manufacturing a vertical channel FET Method of manufacturing a vertical channel FET

1994-02-09

1995-04-04

Thomas, Tom

Fishing, trapping, and vermin destroying

437 35, 437 45, H01L 21266

Patent

active

054037638

ABSTRACT:
A field effect transistor is formed on a side surface of an elevation protruded from the upper surface of a substrate. A gate electrode is formed on the side surface with a gate insulating film therebetween. Source and drain regions are formed in the top of the elevation and the surface of the substrate adjacent to the elevation by ion implantation with the gate electrodes as a mask.

REFERENCES:
patent: 4250519 (1981-02-01), Mogi et al.
patent: 4554570 (1985-11-01), Jastrzebski et al.
patent: 4649406 (1987-03-01), Takemae et al.
patent: 4818715 (1989-04-01), Chao
patent: 4819043 (1989-04-01), Yazawa et al.
patent: 4845539 (1989-07-01), Inoua
patent: 4937641 (1990-06-01), Sunami et al.
patent: 4963504 (1990-10-01), Huang
patent: 5047812 (1991-09-01), Pfiester
patent: 5136534 (1992-08-01), McDavid et al.
patent: 5181088 (1993-01-01), Mikata et al.
Mizuno et al., "High Speed and Highly Reliable Trench MOSFET with Dual Gate", Symp. VLSI Tech. Dig. (1988), pp. 23-24.
IEDM 11-14 Dec. 1988, pp. 222-225, San Francisco, Calif., U.S.; H. Takato et al.; "High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs".

Affiliated with

Also associated with

Rating

Method of manufacturing a vertical channel FET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a vertical channel FET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a vertical channel FET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2380318