Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-03-31
2004-03-16
Niebling, John (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S404000, C438S405000
Reexamination Certificate
active
06706615
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transistor and a method of manufacturing the same. In particular, the present invention relates to a power MOSFET widely used in a power supply circuit or the like and a method of manufacturing the same.
2. Description of the Related Art
FIGS. 29 and 30
show a conventional trench type power MOSFET designated by reference numeral
101
.
FIG. 30
is a cross-sectional view taken along line X—X in FIG.
29
. It is noted that like component members are designated by like reference numerals in
FIGS. 29 and 30
.
This power MOSFET
101
has a semiconductor substrate constituted by successively forming a drain layer
112
composed of an n
−
-type epitaxial layer and a P-body region
113
on an n
+
-type silicon substrate
111
as shown in FIG.
30
.
A plurality of trenches having a rectangular cross section of which bottom portion reaches the drain layer
112
are formed in the P-body region
113
and disposed in parallel to each other. A p
+
-type diffusion region
116
in a predetermined depth from the surface of the P-body region
113
is formed at a position between adjacent trenches. An n
+
-type source region
130
is formed in the periphery of the p
+
-type diffusion region
116
and surrounding an aperture of the trench from the surface of the P-body region
113
to such a depth as not reaching the drain layer
112
.
A gate insulating film
124
is formed on an inner peripheral surface and bottom surface of the trench. A polysilicon gate
127
is formed on a surface of the gate insulating film
124
so that the inside of the trench is filled and that its upper end is positioned higher than the lower end of the source region
130
.
A PSG (phospho-silicate glass) film
131
is formed on top of the polysilicon gate
127
. A source electrode film
137
composed of aluminum is formed so as to cover the PSG film
131
and the surface of the semiconductor substrate. The polysilicon gate
127
and the source electrode film
137
are electrically insulated from each other by the PSG film
131
. Furthermore, a drain electrode film
193
is formed on the bottom surface of the semiconductor substrate.
In a power MOSFET
101
having this structure, when a voltage equal to a threshold voltage or higher is applied between the polysilicon gate
127
and the source electrode film
137
in a state that a high voltage is being applied between the source electrode film
137
and the drain layer
112
, an inversion layer is formed at an interface between the gate insulating film
124
and the P-body region
113
. Thus, a current flows from the drain to the source through the inversion layer.
The abscissa axis (E) of a graph in
FIG. 30
represents an electric field strength when reverse bias voltage is applied between the source electrode film
137
and the drain layer
112
. The ordinate axis (y) represents a position on a line starting at an origin and vertically reaching the n
+
-type silicon substrate
111
where the origin is the surface of the source region
130
in the power MOSFET
101
shown in FIG.
30
.
Line Y—Y in
FIG. 30
is a line starting at one point in the source region
130
and vertically reaching the n
+
-type silicon substrate
111
through the P-body region
113
and the drain layer
112
without passing through the p
+
-type diffusion region
116
. A polygonal line (b) in
FIG. 30
is a graph showing the relationship between a position on line Y—Y and the electric field strength thereat.
As shown in
FIG. 30
, the electric field strength E includes a high electric field intensively applied to a portion of a pn junction formed by the P-body region
113
and the drain layer
112
. To secure a desired avalanche breakdown voltage by decreasing the electric field strength, the concentration of the drain layer
112
can be lowered so that the depletion layer can be easily expanded. In this case, however, a problem arises that the on-resistance of the power MOSFET
101
increases.
SUMMARY OF THE INVENTION
The present invention was accomplished to solve the above-described problem of the prior art. Accordingly, an object of the present invention is to provide a technique by which the on-resistance R
ON
of a transistor of the present invention can be made lower than that of a conventional one even when the transistor has a avalanche breakdown voltage equal to that of the conventional one.
To solve the above problem, a first aspect of the present invention is a transistor comprising a semiconductor substrate having a semiconductor layer, a drain layer of a first conductivity type disposed on the semiconductor layer and an opposite conductive region of a second conductivity type disposed on the drain layer, polysilicon containing impurities of the second conductivity type disposed in part of the drain layer, a gate trench disposed from a surface of the opposite conductive region to the polysilicon, a source region of the first conductivity type formed on the surface of the opposite conductive region at a position adjacent to the gate trench, a gate insulating film positioned on the inner surface of the gate trench and disposed over the drain layer, the opposite conductive region and the source region, and a gate electrode film disposed in the gate trench in tight contact with the gate insulating film and insulated from the polysilicon.
A second aspect of the invention is a transistor according to the first aspect, wherein the polysilicon and the gate electrode film are insulated from each other by the gate insulating film.
A third aspect of the invention is a transistor according to the first aspect, further comprising an insulating film which is disposed between the polysilicon and the drain layer and insulates the polysilicon from the drain layer.
A fourth aspect of the invention is a transistor according to the first aspect, wherein the semiconductor layer is of the first conductivity type.
A fifth aspect of the invention is a transistor according to the first aspect, wherein the semiconductor layer is of the second conductivity type.
A sixth aspect of the invention is a transistor comprising a semiconductor substrate having a semiconductor layer, a drain layer of a first conductivity type disposed on the semiconductor layer and an opposite conductive region of a second conductivity type disposed on the drain layer, a semiconductor material disposed in part of the drain layer and constituted so that a depletion layer can be formed therein, a gate trench disposed from a surface of the opposite conductive region to the semiconductor material, a source region of the first conductivity type formed on the surface of the opposite conductive region at a position adjacent to the gate trench, a gate insulating film positioned on the inner surface of the gate trench and disposed over the drain layer, the opposite conductive region and the source region, and a gate electrode film disposed in the gate trench in tight contact with the gate insulating film and insulated from the semiconductor material, wherein the semiconductor material is filled at the bottom of a deep trench disposed from the surface of the opposite conductive region to the inside of the drain layer, and the gate trench is formed by the surface of the semiconductor material and the inner peripheral surface of the deep trench.
A seventh aspect of the invention is a transistor according to the sixth aspect, wherein the semiconductor material and the gate electrode film are insulated from each other by the gate insulating film.
An eighth aspect of the invention is a transistor according to the sixth aspect, further comprising an insulating film provided on the inner wall surface and the bottom surface of the deep trench, and wherein the semiconductor material is filled at the bottom of the deep trench so as to come into tight contact with the insulating film.
A ninth aspect of the invention is a transistor according to the sixth aspect, wherein the semiconductor material is formed by epitaxial grow
Kitada Mizue
Kunori Shinji
Takemori Toshiyuki
Armstrong, Kratz, Quintos Hanson & Brooks, LLP.
Lindsay Jr. Walter L.
Niebling John
Shindengen Electric Manufacturing Co. Ltd.
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