Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure
Reexamination Certificate
2007-10-09
2007-10-09
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having field effect structure
C438S133000, C257S107000, C257SE27052
Reexamination Certificate
active
11007510
ABSTRACT:
In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.
REFERENCES:
patent: 4876213 (1989-10-01), Pfiester
patent: 4956311 (1990-09-01), Liou et al.
patent: 5126279 (1992-06-01), Roberts
patent: 5399513 (1995-03-01), Liou et al.
patent: 5807759 (1998-09-01), Naem et al.
patent: 5891771 (1999-04-01), Wu et al.
patent: 5902125 (1999-05-01), Wu
patent: 5982017 (1999-11-01), Wu et al.
patent: 5989950 (1999-11-01), Wu
patent: 6001738 (1999-12-01), Lin et al.
patent: 6030863 (2000-02-01), Chang et al.
patent: 6037204 (2000-03-01), Chang et al.
patent: 6110763 (2000-08-01), Temple
patent: 6124177 (2000-09-01), Lin et al.
patent: 6187619 (2001-02-01), Wu
patent: 6229161 (2001-05-01), Nemati et al.
patent: 6242785 (2001-06-01), Hossain et al.
patent: 6258682 (2001-07-01), Tseng
patent: 6261935 (2001-07-01), See et al.
patent: 6284613 (2001-09-01), Subrahmanyam et al.
patent: 6294415 (2001-09-01), Tseng et al.
patent: 6326251 (2001-12-01), Gardner et al.
patent: 6346449 (2002-02-01), Chang et al.
patent: 6350656 (2002-02-01), Lin et al.
patent: 6462359 (2002-10-01), Nemati et al.
U.S. Appl. No. 10/609,185, filed Jun. 26, 2003, Horch, et al.
Mark Rodder and D. Yeakley;Raised Source/Drain MOSFET with Dual Sidewall Spacers; IEEE Electron Device Letters; Mar. 1991; pp. 89-91; vol. 12, No. 3; IEEE.
Hsiang-Jen Huang;Improved Low Temperature Characteristics of P-Channel MOSFETs with Si1-xGexRaised Source and Drain; IEEE Transactions On Electron Devices, vol. 48, No. 8, Aug. 2001, pp. 1627-1632; 0018-9383(01)05680-5 2001 IEEE.
T. Ohguro;High Performance RF Characteristics of Raised Gate/Source/Drain CMOS with Co Salicide; Symposium on VLSI Technology Digest of Technical Papers; 0-7803-4700-6/98 1998 IEEE.
Yang-Kyu Choi;Nanoscale Ultrathin Body PMOSFETs With Raised Selective Germanium Source/Drain; IEEE Electron Device Letters; Sep. 2001; vol. 22, No. 9, pp. 447-448; 0741-3106(01)07740-0 2001 IEEE.
N. Lindert;Quasi-Planar FinFETs with Selectively Grown Germanium Raised Source/Drain; 2001 IEEE International SOI Conference; Oct. 2001; pp. 111-112; 0-7803-6739-1/01 2001 IEEE.
K. De Meyer;Raised Source/Drains with Disposable Spacers for Sub 100 nm CMOS Technologies; Extended Abstracts of International Workshop on Junction Technology 2001; pp. 87-90; ISBN 4-89114-019-4/020-8; 2001 Japan Society of Applied Physics.
Hause Fred
Horch Andrew E.
Estrada Michelle
T-Ram Semiconductor Inc.
Tobergte Nicholas
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