Method of manufacturing a thin film transistor using positive an

Details Method of manufacturing a thin film transistor using positive an Method of manufacturing a thin film transistor using positive an

1989-12-22

1992-08-11

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437101, 437229, H01L 21336, H01L 2147, H01L 29784

Patent

active

051378418

ABSTRACT:
A self-aligned TFT array for liquid crystal display devices and a method of manufacturing the array are disclosed. A protective insulating layer on a semiconductor layer is exactly aligned with a gate electrode. A self-alignment method is used for patterning the protective insulating layer and an impurity-doped semiconductor layer on the semiconductor layer. No lift-off process is necessary.

REFERENCES:
patent: 4386352 (1983-05-01), Nonomura et al.
patent: 4601097 (1986-07-01), Shimbo
patent: 4609930 (1986-09-01), Yamazaki
patent: 4618873 (1986-10-01), Sasano et al.
patent: 4624737 (1986-11-01), Shimbo
patent: 4685195 (1987-08-01), Szydlo et al.
patent: 4700458 (1987-10-01), Suzuki et al.
patent: 4788154 (1988-11-01), Nakamura
patent: 4821092 (1989-04-01), Noguchi
patent: 4862234 (1989-08-01), Koden
patent: 4938567 (1990-07-01), Chartier
patent: 4961629 (1990-10-01), Kato
Snell et al. "Application of Amorphous Silicon Field Effect Transistors in Addressable Liquid Crystal Display Panels", Applied Physics, 1981, pp. 357-362.

Affiliated with

Also associated with

Rating

Method of manufacturing a thin film transistor using positive an does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a thin film transistor using positive an, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a thin film transistor using positive an will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-346127