Method of manufacturing a test circuit on a silicon wafer

Details Method of manufacturing a test circuit on a silicon wafer Method of manufacturing a test circuit on a silicon wafer

1999-10-18

2000-11-14

Graybill, David E.

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

438 18, H01L 2100, G01R 3126

Patent

active

061469084

ABSTRACT:
The invention relates to a method of manufacturing, on a silicon wafer, a plurality of integrated circuits and at least one test circuit, comprising steps of insulation of the silicon wafer by means of a reticle disposed in an exposure chamber provided with a diaphragm which allows to hide the non useful parts of the reticle. According to the invention, the method comprises an insulation (exposure) step performed by means of a reticle (130) comprising an insulation mask region (132) for integrated circuits together with at least one insulation mask region (133, 134, 135) for a test circuit. The insulation step includes one or more insulation steps during which the insulation mask region for test circuit is hidden by the diaphragm, and at least one insulation step during which the insulation mask region for test circuit is uncovered by the diaphragm, while all or part of the insulation mask for integrated circuit is hidden by the diaphragm.

REFERENCES:
patent: 4538105 (1985-08-01), Ausschnitt et al.
patent: 5264377 (1993-11-01), Chesire et al.
patent: 5705299 (1998-01-01), Tew et al.

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