Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1999-10-22
2002-10-08
Knode, Marian C. (Department: 1746)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S745000, C438S689000
Reexamination Certificate
active
06461978
ABSTRACT:
This application claims the benefit of Japanese Patent Application No. 1998-303057, filed on Oct. 23, 1998, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
The present invention relates to an etchant, a method of manufacturing a substrate for electronic device by using an etchant, and an electronic device having the substrate, and especially an etchant in which each layer of wiring formed by stacking an Al layer, or Al alloy layer, and a Ti layer, or Ti alloy layer, can be uniformly etched to a substantially equal etching rate by the etchant.
Al as a wiring material has an advantage of having low resistance, and it is frequently used as the wiring material of an electrode etc. on a substrate of an electronic device.
As an example of the electronic device,
FIG. 12
is a plan view showing a thin film transistor in a conventional thin film transistor LCD.
The thin film transistor
82
comprises a gate electrode
84
formed on a substrate
83
and a gate insulating layer
85
to cover the gate electrode
84
. A semiconductor active layer
86
of an amorphous silicon (hereinafter, “a-Si”) is formed on the gate insulating layer
85
of the upper gate electrode
84
. And a source electrode
88
and a drain electrode
89
are extended on the gate insulating layer
85
or semiconductor active layer
86
wherein ohmic contact layer
87
composed of amorphous silicon having n-type impurity like phosphorus(P)(hereinafter, “n
+
a-Si”) is inserted. Also a passivation layer
90
covering a thin film transistor
82
made up of the source electrode
88
, the drain electrode
89
, and the gate electrode
84
is formed, and a contact hole
91
is formed on the passivation layer
90
of the drain electrode
89
. Further a pixel electrode
92
constituted by a transparent electrode layer of indium tin oxide (hereinafter, “ITO”) electrically connected with the drain electrode
89
through the contact hole
91
is formed.
And the left part of
FIG. 12
shows a sectional view of a gate terminal pad
93
of the gate wiring. A contact hole
95
passing through a gate insulating layer
85
and a passivation layer
90
is formed on the lower pad layer
94
composed of gate wiring material on the substrate
83
, and a upper pad layer
96
constituted by a transparent electrode layer is electrically connected with a lower pad layer
94
through the contact hole
95
. Also a source wiring is of similar structure to the gate wiring.
As mentioned hereto, for example, in the thin film transistor, the transparent electrode layer constituting a gate terminal, a source terminal and a pixel electrode is directly connected with a metal for wiring constituting the gate wiring, the source wiring and the drain electrode.
By the way, in the case of using the Al metal layer as a wiring material in order to reduce the wiring resistance in the electronic device, a hillock is generated. The hillock is generated as a needle-shaped projection on the surface of the Al layer during a heat treatment. The projection is passed through the stacked insulating layer so that a short circuit is generated with another conducting layer, or a poor insulation occurs. Also if the ITO were directly contacted with the Al, oxygen of the ITO should oxidize the Al, as a result, the electric resistance of contact part should be increased.
In order to prevent the above problem, a stacked layer, produced by forming another metal layer like Mo layer or Cr layer on the Al layer (hereinafter, “different metal stacked layer”), has been widely used. In the case of providing a gate electrode
84
in a stacked layer of the different metal from each other, for example, as shown in
FIG. 14A
, a photo-mask
97
of a desired pattern is formed on the surface of stacked layer
84
c
stacking an Mo layer
84
b
on the Al layer
84
a
formed on the substrate
83
by photolithography. And then, the stacked layer
84
c
is obtained from uniform etching by using an etchant having H
3
PO
4
of 80 wt %, HNO
3
, CH
3
COOH and H
2
O.
By the way, in the case that it is patterned by uniform etching of the different metal stacked layer, a battery reaction of the etchant is generated by the potential difference between the metal layers, and an under-cut is generated, in which a line width of the Al layer
84
a
in the lower layer is shorter than a line width of the Mo layer
84
b
in the upper layer as shown in
FIG. 14B
, because the Al layer in the lower layer is more quickly etched than the Mo layer in the upper layer. Also a problem of poor insulation enduring press may be generated.
Therefore, in order to solve these problems, after the uniform etching, sunscreen-shaped Mo layer
84
b
can be patterned by added etching by using an uric acid.
SUMMARY OF THE INVENTION
By the way, in the conventional method of manufacturing a substrate for an electronic device which is provided with the different metal stacked layer, the yield will be bad, the manufacturing process will be lengthened, and the cost will rise because at least two etching processes are needed. Further if adding etching were executed as mentioned above, the Mo layer in the upper layer should be a little more quickly etched than the Al layer in the lower layer, and as a result, as shown in
FIG. 14C
, the Al layer in the lower layer would be projected, and it is difficult to control a line width of wiring in the upper and lower layers.
Also, another method of forming a gate electrode in the different metal stacked layer, as shown in
FIG. 15A
, comprises the steps of: providing an Al layer
84
a
on the substrate
83
; coating photoresist
97
on the surface of Al layer
84
a
; executing photolithography; and etching, as shown in
FIG. 15B
, so that an Al layer
84
a
of a desired line width is obtained. Subsequently the method comprises the steps of: covering the Al layer
84
a
by a Mo layer
84
b
, as shown in
FIG. 15C
; forming by photolithography a photo-mask
98
of a desired pattern, as shown in
FIG. 15D
; and then etching. By the way, at least a double etching process is needed like the conventional method, so that a problem is generated in this method, also. And the stacked wiring has a structure in which the Al layer
84
a
in the lower layer is covered with an Mo layer
84
b
in the upper layer, as shown in
FIG. 15E
, so that the line width in the upper layer is necessarily larger than the line width in the lower layer. As a result it is difficult to control the line width of wiring in the upper layer and lower layer.
The present invention is constituted with regard to the problems outlined above. In forming a stacked layer (formed by stacking a different metal layer on an Al layer, or Al alloy layer, having a lower resistance, as a wiring material), the present invention provides: an etchant which can etch with a substantially equal etching rate, by etching only one time, each metal layer of the stacked layer; a method of manufacturing a substrate for an electronic device by using the etchant; and an electronic device having the substrate.
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Knode Marian C.
LG. Philips LCD Co. Ltd.
McKenna Long & Aldridge LLP
Zervigon Rudy
LandOfFree
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