Method of manufacturing a strained semiconductor layer,...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C257S326000, C257S616000, C438S222000, C438S569000, C438S933000

Reexamination Certificate

active

07554138

ABSTRACT:
The invention relates to a method of manufacturing a semiconductor strained layer and to a method of manufacturing a semiconductor device (10) in which a semiconductor body (11) of silicon is provided, at a surface thereof, with a first semiconductor layer (1) having a lattice of a mixed crystal of silicon and germanium and a thickness such that the lattice is substantially relaxed, and on top of the first semiconductor layer (1) a second semiconductor layer (2) is provided comprising strained silicon, in which layer (2) a part of the semiconductor device (10) is formed, and wherein measures are taken to avoid reduction of the effective thickness of the strained silicon layer (2) during subsequent processing needed to form the semiconductor device (10), said measures comprising the use of a third layer (3) having a lattice of a mixed crystal of silicon and germanium. According to the invention, the third layer (3) is thin and positioned within the second layer (2) close to the interface between the first and second semiconductor layers (1,2). In this way the resulting thickness of the strained silicon layer (2), after subsequent formation of the MOSFET, can be increased, resulting in a MOSFET with better high-frequency properties. The invention also comprises a device obtained with a method according to the invention and a semiconductor substrate structure suitable for use in such a method.

REFERENCES:
patent: 6900103 (2005-05-01), Fitzgerald
patent: 2002/0123183 (2002-09-01), Fitzgerald
patent: 2003/0131787 (2003-07-01), Linares et al.
patent: 37 31 000 (1989-03-01), None
patent: 0 307 850 (1989-03-01), None
patent: 1 020 900 (2000-07-01), None
Carns T K et al: “A Novel High Speed, High Density SRAM Cell Utilizing A Bistable GESI/SI Tunnel Diode”; Electron Devices Meeting 1994; Tech. Digest San Francisco Dec. 11-14, 1994; pp. 381-384.

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