Method of manufacturing a stacked semiconductor device

Details Method of manufacturing a stacked semiconductor device Method of manufacturing a stacked semiconductor device

2005-02-08

2005-02-08

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S455000, C438S456000

Reexamination Certificate

active

06852570

ABSTRACT:
A method of manufacturing a semiconductor device which can solve a problem in which a wafer is warped by the influence of thermal contraction of a sealing resin due to a difference in thermal contraction between the wafer and the sealing resin. A second wafer on which electrodes are formed is stacked on a first wafer such that the electrodes of the second wafer are electrically connected to the electrodes formed on the first wafer, a portion between the first wafer and the second wafer is sealed with a resin, the second wafer and the sealing resin are half cut to expose the conductive posts from the sealing resin, conductive bumps for performing electric connection to an external circuit are formed on the exposed conductive posts, and the wafer is diced into independent semiconductor devices. In the resin sealing step, since both the first and second semiconductor elements are stacked in wafer states, a problem in which the wafers are warped by the influence of thermal contraction of the sealing resin due to a difference in thermal contraction between the wafers and the sealing resin can be solved.

REFERENCES:
patent: 5939817 (1999-08-01), Takado
patent: 6004867 (1999-12-01), Kim et al.
patent: 6084308 (2000-07-01), Kelkar et al.
patent: 6201302 (2001-03-01), Tzu
patent: 6204562 (2001-03-01), Ho et al.
patent: 6236115 (2001-05-01), Gaynes et al.
patent: 6348728 (2002-02-01), Aiba et al.
patent: 6429511 (2002-08-01), Ruby et al.
patent: 6504253 (2003-01-01), Mastromatteo et al.
patent: 6525414 (2003-02-01), Shiraishi et al.
patent: 6559531 (2003-05-01), Sutherland
patent: 6611055 (2003-08-01), Hashemi
patent: 6627988 (2003-09-01), Andoh
patent: 6670206 (2003-12-01), Kim et al.
patent: 20020070458 (2002-06-01), Tago
patent: 20020094601 (2002-07-01), Su et al.
patent: 20020125556 (2002-09-01), Oh et al.
patent: 20020180027 (2002-12-01), Yamaguchi et al.
patent: 20030116859 (2003-06-01), Hashimoto
patent: 20030189251 (2003-10-01), Terui et al.
patent: 20030197291 (2003-10-01), Hasegawa
patent: 20040029360 (2004-02-01), Geefay et al.
patent: 61-089657 (1986-05-01), None
patent: 11-177020 (1999-07-01), None
patent: 2001-257310 (2001-09-01), None
patent: 2001345336 (2001-12-01), None
patent: WO9840915 (1998-09-01), None
U.S. Appl. No. 09/797,907, ‘Semiconductor Device and the Method for Manufacturing the Same’.

Affiliated with

Also associated with

Rating

Method of manufacturing a stacked semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a stacked semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a stacked semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3450844