Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1995-09-25
1998-09-15
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438253, H01L 2120, H01L 218242
Patent
active
058077820
ABSTRACT:
A method for manufacturing a stacked capacitor having fin-shaped electrodes with increased capacitance on a dynamic random access memory (DRAM) cell, was achieved. The invention eliminates the need for a silicon nitride etch stop layer, which is known to cause stress in the substrate and lead to defects. The capacitor bottom electrodes having fin shaped portions is fabricated by depositing a multilayer of alternate layers of silicon oxide and doped polysilicon on a partially completed DRAM device having FETs. After forming, with single masking step, the node contacts to the substrate in the multilayer and depositing another doped polysilicon layer, the polysilicon layers and oxide layer are patterned to form the electrodes. An important feature of this invention is that the patterned multilayer is etched to the silicon oxide layer over the bottom polysilicon layer and then the silicon oxide layer(s) are isotropically etched (e.g. in HF) to form the fin capacitor. The fin structure is then used as a mask to anisotropically etch the bottom polysilicon layer, and thereby complete and electrically isolate the bottom fin-shaped electrodes. The capacitor is completed by forming the inter-electrode dielectric and depositing a top electrode layer.
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Koh Chao-Ming
Liang Wen-Jya
Liu Bin
Ackerman Stephen B.
Bowers Jr. Charles L.
Saile George O.
Thomas Toniae M.
Vanguard International Semiconductor Corporation
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