Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-04-28
1998-12-22
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438224, 438561, 438563, H01L 2176
Patent
active
058519009
ABSTRACT:
A new method for forming shallow trench isolation is disclosed herein. A pad oxide layer and a silicon nitride layer are formed on a wafer, respectively. A plurality of trenches are created in the wafer. Then, a SAC layer is formed on an N-well. A BSG layer is formed on a P-well and the N-well. A thermal process is used to form a channel stop in the P-well. Then, the BSG layer and the SAC layer are removed. Subsequently, a LPD oxide layer is deposited in the trenches. Then, a CMP process is used to polish the LPD oxide layer for planarization. The pad oxide layer and the silicon nitride layer are removed. Next, a gate oxide layer is formed on the wafer.
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Chu Chih-Hsun
Yang Ching-Nan
Fourson George
Mosel Vitelic Inc.
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