Method of manufacturing a semiconductor wafer level package

Details Method of manufacturing a semiconductor wafer level package Method of manufacturing a semiconductor wafer level package

2000-09-08

2002-10-15

Whitehead, Jr., Carl (Department: 2826)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C438S126000, C257S687000

Reexamination Certificate

active

06465281

ABSTRACT:

FIELD OF THE INVENTION
This present invention relates to the wafer-scale packaging of monolithically integrated sensors and actuators and of integrated circuits in general.
BACKGROUND OF THE INVENTION
The advancement and miniaturization of integrated circuit technologies through the application of micromachining processes derived from standard microelectronic fabrication technologies has required the introduction of new packaging techniques to protect various elements of the sensor system from unwanted exposure during manufacturing or in the system application. Ideally, these techniques would be applied at the wafer scale, prior to die singulation, as has been described in U.S. Pat. No. 5,323,051. Wafer scale packaging provides significant enhancements for manufacturing and has resulted in the introduction of many micromachined sensor components more difficult or impossible to produce with other techniques.
The performance enhancement gained through the monolithic integration of control circuitry along with micromachined sensing elements again taxes the potential of wafer scale packaging techniques. Wafer scale packaging using a glass frit as the bonding medium requires temperatures not typically compatible with standard microelectronics processing for the bond process, and often involves frit materials containing elemental components deleterious to active circuitry. Even with the resolution of such limitations, neither performance nor area utilization is enhanced significantly if the wafer scale packaging requires unique bond areas.
Accordingly, there exists a need for a wafer level package in which glass frit may be formed in contact with active components of a semiconductor device. Further, such a semiconductor package, that may or may not contain a cap wafer, provides a reliable device without compromising the characteristics of the components.
SUMMARY OF THE INVENTION
This present invention provides a semiconductor wafer-level package in which glass frit is formed directly in contact with the devices or active circuitry in the monolithic device. This could be embodied using wafer bond or by direct application of glass frit to the devices. This package may be used to encapsulate a monolithically-integrated sensor structure, to protect an integrated circuit from unwanted exposure to environmental or electromagnetic interactions, or to create wafer-scale protected integrated circuits and systems for flip-chip packaging applications. A preferred embodiment includes a cap wafer bonded to the semiconductor substrate, which may include integrated circuits and sensors. This bond is formed using a pattern of frit glass as a pattern such that any sealed volumes formed by the cap wafer, frit glass, and semiconductor substrate are hermetically sealed. Integrated circuits (devices), can exist beneath the frit glass seal. Another preferred embodiment includes direct application of a pattern of glass frit to a semiconductor substrate such that regions of the substrate are hermetically sealed. Integrated circuits (devices) can exist directly beneath the frit glass.


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