Fishing – trapping – and vermin destroying
Patent
1994-06-08
1996-05-07
Thomas, Tom
Fishing, trapping, and vermin destroying
437 52, 437239, H01L 218247
Patent
active
055146074
ABSTRACT:
When the surfaces of a selection gate electrode and a floating gate electrode are thermally oxidized with the selection gate electrode disposed below the floating gate electrode, the thickness of a gate oxide film formed on the selection gate electrode can be made larger than that of a gate oxide film formed on the other portion. As a result, the coupling ratio of a memory transistor can be increased. Thus, the coupling ratio can be adequately increased by partly increasing the thickness of the insulation film between the floating gate electrode and the semiconductor substrate.
REFERENCES:
patent: 4649520 (1987-03-01), Eitan
patent: 4701776 (1987-10-01), Perlegos et al.
patent: 4949140 (1990-08-01), Tam
patent: 4988635 (1991-01-01), Ajika et al.
patent: 4989053 (1991-01-01), Shelton
patent: 4989054 (1991-01-01), Arima et al.
patent: 5017979 (1991-05-01), Fujii et al.
Lander et al., "Recessed Gate One-Device Cell Memory Array", IBM Technical Disclosure Bulletin, vol. 18, No. 12, May 1976, New York, US, pp. 3951-3952.
Arima et al., "A High Density Performance Cell For 4M Bit Full Feature Electrically Erasable/Programmable Read-Only Memory", Japanese Journal of Applied Physics, vol. 30, No. 3A, Mar. 1, 1991, Tokyo, JP, pp. 334-337.
Kabushiki Kaisha Toshiba
Thomas Tom
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