Method of manufacturing a semiconductor integrated circuit devic

Details Method of manufacturing a semiconductor integrated circuit devic Method of manufacturing a semiconductor integrated circuit devic

1975-09-29

1977-09-20

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 29580, 148 15, 148187, 156647, 357 22, 357 43, 357 55, H01L 2122, H01L 21306, H01L 2976

Patent

active

040494764

ABSTRACT:
A method of manufacturing a semiconductor integrated circuit device, which includes at least one junction field-effect transistor and at least one bipolar transistor, is characterized in that a groove portion is formed by chemically etching a part of a diffused layer for the channel region of the junction field-effect transistor, and that a layer for the gate of the junction field-effect transistor having a conductivity type to opposite to that of the channel region is formed by diffusion in the diffused layer of the channel region beneath the groove portion, whereby the pinch-off voltage V.sub.p of the junction field-effect transistor is made as small as possible and is also made smaller than the base-emitter reverse withstand voltage V.sub.BEO of the bipolar transistor.

REFERENCES:
patent: 3474308 (1969-10-01), Kronlage
patent: 3538399 (1970-11-01), Bresee et al.
patent: 3576475 (1971-04-01), Kronlage
patent: 3594241 (1971-07-01), Bresee
patent: 3796612 (1974-03-01), Allison
patent: 3924265 (1975-12-01), Rodgers
patent: 3930300 (1976-01-01), Nicolay

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