Method of manufacturing a semiconductor integrated circuit devic

Details Method of manufacturing a semiconductor integrated circuit devic Method of manufacturing a semiconductor integrated circuit devic

1994-07-08

1996-04-30

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 57, 437 59, 437162, 437200, H01L 21265, H01L 218238

Patent

active

055124976

ABSTRACT:
Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

REFERENCES:
patent: 5354699 (1994-10-01), Ikeda

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