Method of manufacturing a semiconductor integrated circuit...

Details Method of manufacturing a semiconductor integrated circuit... Method of manufacturing a semiconductor integrated circuit...

2006-04-18

2006-04-18

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S622000, C438S629000, C438S706000

Reexamination Certificate

active

07030030

ABSTRACT:
A method is provided for manufacturing an integrated circuit device having a plurality of wiring layers including a first wiring layer which is not the upper most layer among the plurality of wiring layers and a second wiring layer higher than the first wiring layer in the plurality of wiring layers. An interlayer dielectric film is provided to cover the first wiring layer. Holes are then formed in the interlayer dielectric film and a mask film is formed to cover some of the holes. Etching using the mask film is then carried out and an insulating film formed on the interlayer dielectric film is removed, including the bottoms and/or insides of the holes. The mask film is then removed and a conductive member is formed inside the holes.

REFERENCES:
patent: 5272600 (1993-12-01), Carey
patent: 6165899 (2000-12-01), Matumoto
patent: 6305002 (2001-10-01), Uchida
patent: 6362528 (2002-03-01), Anand
patent: 59-72152 (1984-04-01), None
patent: 5-283611 (1993-10-01), None
patent: 10-22455 (1998-01-01), None

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