Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2005-09-27
2005-09-27
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S010000, C438S130000, C438S215000, C438S281000, C438S467000, C438S601000
Reexamination Certificate
active
06949416
ABSTRACT:
Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.
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Anjo Ichiro
Miyamoto Toshio
Nishimura Asao
Yamaguchi Yoshihide
Antonelli, Terry Stout and Kraus, LLP.
Fourson George
García Joannie Adelle
Renesas Technology Corp.
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