Method of manufacturing a semiconductor element

Fishing – trapping – and vermin destroying

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437187, 437 21, 427487, 427485, 148DIG45, H01L 21765

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active

054628865

ABSTRACT:
A method of manufacturing a semiconductor element such as a thin film transistor or a photo diode, in which a voltage is applied to an organic insulating layer in the direction vertical to a substrate during a coating process of polyimide constituting the interlayer insulating layer formed over a semiconductor layer, a prebaking process for initial hardening which immediately follows the coating process, and a postbaking process after the pattern formation of the interlayer insulating layer.

REFERENCES:
patent: 4704299 (1987-11-01), Wielonski et al.
patent: 4983546 (1991-01-01), Hyun et al.
patent: 4999215 (1991-03-01), Akagi et al.
patent: 5270267 (1993-12-01), Ouellet
Ogawa, "Degradation of Sub-Threshold Characteristics in a--Si TFT with Polyimide Passivation," Extended Abstracts of the 22nd (1990 International) Conference on Solid State Devices and Materials, Sendai, 1990.

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