Semiconductor device manufacturing: process – Semiconductor substrate dicing – With attachment to temporary support or carrier
Reexamination Certificate
2000-01-19
2004-05-04
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
With attachment to temporary support or carrier
Reexamination Certificate
active
06730579
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a manufacturing method os a semiconductor device, and more specifically concerns a polishing process and a dicing process of a semiconductor wafer.
BACKGROUND OF THE INVENTION
[Prior Art Example 1]
Referring to FIG.
11
and FIGS.
12
(
a
) to FIG.
12
(
g
), the following description will discuss processes from the rear-face polishing process to the dicing process of a semiconductor wafer disclosed in Japanese Laid-Open Patent Application No. 22358/1995 (Tokukaihei 7-22358, published on Jan. 24, 1995).
Before a rear-face polishing process, a semiconductor wafer
101
is subjected to an electrical test by means of probing (hereinafter referred to as “wafer test”) (S
101
, see FIG.
12
(
a
)) and a protection and reinforcing tape
102
is affixed onto the front face (element formation face) thereof (see S
102
, FIG.
12
(
b
)). The protection and reinforcing tape
102
is formed by, for example, laminating an acrylic bonding agent onto a polyethylene terephthalate (PET) film.
After polishing the rear face of the semiconductor wafer
101
(S
103
, FIG.
12
(
c
)), the rear face of the semiconductor wafer
103
is affixed onto a dicing tape
106
through a carrier frame
105
with the protection and reinforcing tape
102
being affixed on the front face thereof (S
104
, FIG.
12
(
d
)).
Next, the protection and reinforcing tape
102
is separated from the front face of the semiconductor wafer
103
(S
105
, FIG.
12
(
e
)). In this case, as illustrated in FIG.
12
(
e
), a separation tape
104
, which has a greater adhesive force than the adhesive force between the protection and reinforcing tape
102
and the semiconductor wafer
103
, is used so as to separate the protection and reinforcing tape
102
.
Successively, after washing residual bonding agent from the front face of the semiconductor wafer
103
by means of ultrasonic washing with pure water (S
106
, FIG.
12
(
f
)), the semiconductor wafer
103
is full-cut or semi-full-cut through a dicing process using a diamond wheel so that a semiconductor chip
107
having a predetermined size is formed (S
107
, FIG.
12
(
g
)).
Next, the sequence proceeds to a die bonding process. In the die bonding process, only one of the semiconductor chips
107
is pushed up by a pin from the rear face of the semiconductor wafer
103
through the dicing tape
106
so that this is subjected to a die bonding process by using the die bonding collet
103
(S
108
). Here, those semiconductor wafers
103
that have been subjected to the semi-full dicing process undergo the die bonding process after a breaking process.
In the following Prior Art Examples 2 through 4, an explanation will be given of methods for carrying out chemical etching on the polished rear face and dicing cut face of the semiconductor wafer.
[Prior Art Example 2]
Referring to
FIG. 13
, an explanation will be given of a method for chemically etching the rear polished face of the semiconductor wafer disclosed in Japanese Laid-Open Patent Application No. 201805/1995 (Tokukaihei 7-201805 (published on Aug. 4, 1995).
The front face (element formation face) of the semiconductor wafer
103
having the polished rear face is covered with a protection film
108
(for example, a rubber tape, etc.), and this is attached to a securing base
109
that is freely rotated by a rotation axis
110
, with the rear face of the semiconductor wafer
103
facing up. While the wafer securing base
109
is being rotated at a high speed, etchant (for example, a hydrogen fluoride etchant in the case of a semiconductor
103
of Si series) is discharged from an etchant spouting nozzle
111
onto the rear face of the semiconductor wafer
103
that faces up, and at the same time, a cooling fluid (for example, pure water or nitrogen gas), which is inert to the etching reaction, is discharged through a cooling fluid spouting nozzle
112
onto the front face of the semiconductor wafer
103
that faces down; thus, the chemical etching process for eliminating stress resulting from polishing is carried out.
[Prior Art Example 3]
Referring to FIGS.
14
(
a
) through
14
(
d
), an explanation will be given of a method for chemically etching the dicing cut face disclosed in Japanese Laid-Open Patent Application No. 161665/1995 (Tokukaihei 7-161665, published Jun. 23, 1995).
First, a novolak resin is dropped onto the front face of a semiconductor wafer
103
and this is rotated so as to form a protective film
113
(FIG.
14
(
a
)). Next, a dicing sheet (dicing tape
106
) is affixed to the front face (element formation face) of the semiconductor wafer
103
, and a dicing process is carried out by using a blade so as to divide it into semiconductor chips
107
(FIG.
14
(
b
)). The semiconductor chips
107
thus cut off are immersed into an etchant
114
of a sulfuric-acid type, an ammonia type, etc. so that a machining-affected layer on the cut face
107
a
is removed (FIG.
14
(
c
)). Thereafter, the semiconductor chips
107
are immersed and washed in a solvent
115
such as acetone so that the protective layer
113
formed on the front face of the semiconductor chip
107
is removed (FIG.
14
(
c
)).
[Prior Art Example 4]
Referring to FIG.
15
and FIG.
16
(
a
) to FIG.
16
(
f
), an explanation will be given of a method for carrying out a rear-face polishing process by chemical etching after a dicing process, which is disclosed in Japanese Laid-Open Patent Application No. 117445/1988 (Tokukaishou 63-117445, published May 21, 1988).
After completion of an IC formation process (S
111
, FIG.
16
(
a
)), a bump
116
is formed by means of electrolytic plating through a bumping process on each IC of the semiconductor wafer
101
prior to polishing (S
112
, FIG.
16
(
b
)). Next, a groove having a predetermined depth is formed along ICs from the front face (element formation face) by a dicing process (S
113
, FIG.
16
(
c
)). Successively, after a wax applying process in which the front face of the semiconductor wafer
101
is coated with wax
117
having chemical etching resistance (S
114
, FIG.
16
(
d
)), the semiconductor wafer
101
is immersed in a chemical etchant
118
in an etching process so that the rear face thereof is etched so as to have a predetermined thickness (S
115
, FIG.
16
(
e
)). Then, the semiconductor wafer
103
is washed by water so as to wash the chemical etchant
118
away, and the wax
117
is removed by a solvent. Thereafter, the semiconductor wafer
103
is subjected to a breaking process so as to separate it into semiconductor chips
107
(S
116
, FIG.
16
(
f
)).
[Prior Art Example 5]
Referring to FIG.
17
(
a
) to FIG.
17
(
e
), an explanation will be given of a manufacturing method for semiconductor chins disclosed in Japanese Examined Patent Publication No. 2737859/1998 (published on Jan. 16, 1998).
First, a semiconductor wafer
101
having a wafer surface pattern formed thereon is checked to see its characteristics (FIG.
17
(
a
)). Then, the wafer
101
is subjected to a semi-full dicing process so as to form the shape of individual chips thereon with a portion x corresponding to approximately half the thickness left from the wafer element formation face (FIG.
17
(
b
)). Thereafter, stains and water adhering to the wafer
101
are removed. Next, a base film
122
is affixed thereon with a bonding agent
121
so as to secure the chips during a rear-face polishing process on the next step (FIG.
17
(
c
)). Moreover, a fixing jig
123
is placed on the periphery of the wafer
101
. Then, the wafer
101
is polished from the rear face side up to a predetermined amount so as to separate it into individual chips
107
(FIG.
17
(
d
)). Thereafter, stains and water adhering to the wafer
101
are removed.
Next, the chips
107
, bonded to the base film
122
, are pushed from the base film
122
side by a pushing jig
124
so that they are allowed to adhere to a joining material
126
that adheres to a die pad
125
shifting in the arrow direction; thus, the chips
107
are separat
Duy Mai Anh
Fahmy Wael
Nixon & Vanderhye PC
Sharp Kabushiki Kaisha
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