Fishing – trapping – and vermin destroying
Patent
1992-12-21
1995-01-31
Fourson, George
Fishing, trapping, and vermin destroying
437 41, 437186, H01L 21265
Patent
active
053858573
ABSTRACT:
A method of manufacturing a semiconductor device having a field effect transistor and a device manufactured by this method in which a high packing density can be realized. The field effect transistor includes a gate electrode (31,41) which is separated from a channel region by a first insulating layer (8) and is entirely surrounded by insulating material. For this purpose, a conductive layer (9) which is to form a gate electrode (31,41) is covered with a second insulating layer (10) and both layers are subsequently given the same pattern at least at the area of the channel region. As a result, the gate electrode (31,41) is covered at the upper side with a portion of the second insulating layer (10). The gate electrode (31,41) is laterally insulated by the provision of a third insulating layer (13) which is subsequently etched back anisotropically, whereby a portion (14) thereof remains intact afterwards alongside the side wall of the gate electrode (31,41). At least the source (32,42) or the drain (33,43) of the transistor is provided with an electrical connection (20) which makes contact through a contact window (19) in a further insulating layer (19). Due to the complete insulation of the gate electrode (31,41), the contact window (19) is allowed to overlap the associated gate electrode (31,41), so no alignment tolerances need be taken into account relative to the gate electrode (31,41) for forming this window (19).
REFERENCES:
patent: 4364167 (1982-12-01), Donley
patent: 4786609 (1988-11-01), Chen
patent: 4992389 (1991-02-01), Ogura et al.
patent: 5153144 (1992-10-01), Komori et al.
patent: 5192992 (1993-03-01), Kim et al.
patent: 5217923 (1993-06-01), Suguro
patent: 5219777 (1993-06-01), Kang
patent: 5229326 (1993-07-01), Dennison et al.
Biren Steven R.
Fourson George
Mason David
U.S. Philips Corporation
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