Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2007-01-02
2007-01-02
Lindsay, Jr., Walter (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257S019000, C257S055000, C257S063000, C257S065000, C257SE21546
Reexamination Certificate
active
10529962
ABSTRACT:
A method of manufacturing a semiconductor device comprising a silicon body (1) having a surface (4) provided with field isolation regions (2) enclosing active regions (3). In this method, on the surface of the silicon body there is formed an auxiliary layer (5) of a material on which, during an oxidation treatment, a thicker layer of silicon oxide is formed than on the silicon of the silicon body. Here, an auxiliary layer comprising silicon and germanium is formed on the surface, said auxiliary layer preferably being a layer of SixGe1−x−yCy, where 0.70<x<0.95 and y<0.05. Next, at the location of the field isolation regions to be formed, windows (9) are formed in the auxiliary layer and trenches (11) are formed in the silicon body. Next, on the walls (12) of the trenches, a silicon oxide layer (13) is provided and on the walls (10) of the windows a silicon oxide layer (14) is provided, both being formed by an oxidation treatment. The auxiliary layer is not oxidized throughout its thickness. After the oxidation treatment, a layer of insulating material (18) is deposited which fills the trenches and windows completely. Then, successively, a planarization treatment is carried out until the non-oxidized part of the auxiliary layer (17) is exposed, and the exposed part of the auxiliary layer is removed. Thus, field isolation regions (2) are formed having an edge (19) extending above the active regions (3).
REFERENCES:
patent: 5834358 (1998-11-01), Pan et al.
patent: 5837612 (1998-11-01), Ajuria et al.
patent: 6413828 (2002-07-01), Lam
patent: 6545299 (2003-04-01), Peterson et al.
patent: 2001/0029083 (2001-10-01), Chuang et al.
Ravit Claire
Rooyackers Rita Victoire Theodosie
Schmitz Jurriaan
Lee Cheung
Lindsay, Jr. Walter
NXP B.V.
Zawilski Peter
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