Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2001-02-20
2002-11-12
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S406000, C438S411000, C438S421000, C438S456000, C438S619000
Reexamination Certificate
active
06479366
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating such semiconductor device. The invention is particularly well adapted for semiconductor devices having various interconnection wiring layers, such as logic LSIs and DRAMs.
2. Description of the Related Art
In association with recent trend towards the miniaturization and higher integration of semiconductor elements, the distance between a plurality of adjacent interconnection runners is reduced, and this has imposed the problem of increased RC (resistance and capacitance) delay in interconnections caused by increased parasitic capacitance between interconnection runners. To reduce the parasitic capacitances between interconnections most effectively, attempts have been made to provide an air gap between a plurality of interconnection runners arranged on a single layer.
For example, JP-A-7-45701 discloses a method of fabricating a semiconductor device involving the steps of forming a plurality of interconnections on a single. layer, forming a solid film (ice) by cooling with a liquid; removing the solid film until the interconnection portions are exposed, forming a coarse insulating film having a large shrinking rate, evaporating the solid film through the coarse insulating film by vaporizing the solid film by heat or the like, and forming a dense insulating film having a shrinking rate which is smaller than that of the coarse insulating film. This method provides the air gap between interconnections, but brings about, at the same time, a fear that the residual moisture will corrode the interconnections
Similarly, JP-A-9-172068 discloses a fabrication method using an organic resin film as the solid film in place of ice and using an organic SOG (spin on glass) as the coarse insulating film and involving the step of removing the organic resin film through the organic SOG film by means of an
0
2
plasma process or the like. However, it is extremely difficult to remove the organic resin film completely.
Further, JP-A-9-129726 discloses a semiconductor device of a multilevel metallization (wiring) structure in which first and second interconnection wiring layers formed over the first interconnection wiring layers are arranged on a semiconductor substrate. The structural feature of this semiconductor device is such that a vacuum or a gas such as air is present between a plurality of the first interconnection wiring layers arranged on a single layer. To fabricate this semiconductor device, an interlayer insulating film composed of a polyimide film is adhered onto the first interconnection wiring layers, and then etched using a photoresist as a mask to form throughholes. Then, a tungsten plug is formed within each throughhole. Thereafter, an aluminum alloy film is deposited on the resultant, and then etched using a photoresist as a mask to form the second interconnection wiring layers. This fabrication method also provides an air gap between interconnection wiring layers, but still imposes problems since the polyimide film is less heat-resistant and degasses in large amounts. In addition, the polyimide film must have a certain thickness to be adhered onto the first interconnection wiring layers.
Furthermore, JP-A-9-186232 discloses a method of fabricating a semiconductor device involving the steps of forming a first interlayer insulating film on the surfaces of first interconnection wiring layers formed on a semiconductor substrate, forming a second interlayer insulating film so as to bury recesses formed in the first interlayer insulating film, forming a third interlayer insulating film that is deposited on both the first and second interlayer insulating films, and forming cavities in the recesses first by etching the third interlayer insulating film using a throughhole-patterned masking resist and then by etching the second interlayer insulating film exposed by the preceding etching process to thereby remove the second interlayer insulating film buried in the recesses. However, an air gap cannot be provided in all the spaces between the first interconnection wiring layers since the first interlayer insulating film remains on the first interconnection wiring layers.
SUMMARY OF THE INVENTION
The object of the present invention is, therefore, to provide a highly reliable semiconductor device capable of high-speed operation by easily and reliably controlling parasitic capacitances between interconnection metal lines arranged accurately and adequately adjacent to each other so that recent needs for further miniaturization and higher integration of semiconductor elements can be met.
To achieve the above object, a first aspect of the invention provides a semiconductor device that comprises a semiconductor substrate; a plurality of conductive films formed over the semiconductor substrate; an insulating film adhered onto the plurality of conductive films so as to cover the plurality of conductive films, an air gap being provided between the plurality of conductive films so that the plurality of conductive films are insulated through the air gap; and a nitride film formed on the insulating film.
Further, a second aspect of the invention provides a semiconductor device that comprises a semiconductor substrate; a plurality of conductive films formed over the semiconductor substrate; an insulating film adhered onto the plurality of conductive films so as to cover the plurality of conductive films, an air gap being provided between the plurality of conductive films so that the plurality of conductive films are insulated through the air gap, the insulating film including a film selected from the group consisting of a TEOS (tetra ethoxy silane) plasma silicon oxide film, a silicon nitride film and a BPSG (boro-phospho silicate glass) film.
Still further, a method of fabricating a semiconductor device according to the present invention comprises the steps of forming an interlayer insulating film over a semiconductor substrate; forming a plurality of conductive films on the interlayer insulating film; forming a first insulating film on a base film; bonding the first insulating film onto the plurality of conductive films together with the film so as to maintain an air gap between the plurality of conductive-films; and leaving only the first insulating film on the plurality of conductive films by separating the base film from the first insulating film.
According to the method of fabricating a semiconductor device of the invention, the first insulating film is adhered onto the plurality of conductive films (interconnection wiring layers) patterned on the interlayer insulating film or the like by pressing such as thermocompression bonding or the like using the film that has the first insulating film arranged on its surface. During the deposition, the first insulating film is formed so as to cover only the upper surfaces of the interconnection wiring layers, so that the material of the first insulating film does not enter into the space between interconnection metal lines and hence an air gap is provided between adjacent interconnection metal lines. Since the first insulating film is formed on the interconnection layers by pressing, the air gap is provided in the space between the interconnection metal lines easily and reliably to ensure sufficient insulation between the interconnections even if the interconnection wiring layers become further miniaturized in size and a extremely complicated in shape.
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patent: 5896276 (
Connolly Bove & Lodge & Hutz LLP
Malsawma Lex H.
Nippon Steel Corporation
Smith Matthew
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