Method of manufacturing a semiconductor device with a planar int

Details Method of manufacturing a semiconductor device with a planar int Method of manufacturing a semiconductor device with a planar int

1989-05-18

1991-12-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437235, 437982, 148DIG133, H01L 21467

Patent

active

050772384

ABSTRACT:
A method of manufacturing a semiconductor device in which an element is flattened by improving a technique of forming an interlayer insulating film. A thick insulating film having a film thickness necessary for a convexo-concave pattern to be flattened is deposited on a semiconductor substrate comprising the convexo-concave pattern of an element, a wiring and the like. Then, the thick insulating film is etched until it becomes a predetermined film thickness to form an interlayer insulating film having a predetermined film thickness from said thick insulating film. At this time, since acid and water are attached on the surface of the interlayer insulating film, a new film is formed on the surface of the interlayer insulating film to cover this water and acid. Then, a resist pattern having a desired configuration is formed on this new film. A contact hole is formed on the interlayer insulating film using this resist pattern. Thereafter, a wiring pattern electrically connected to the element is formed on the interlayer insulating film through the contact hole. According to this method, since the acid and water attached on the interlayer insulating film are covered with the new film, the adhesion between the interlayer insulating film and the resist is improved. As a result, the contact hole can be opened reliably, whereby the element is surely connected to the wiring pattern and a semiconductor device can be provided with high reliability.

REFERENCES:
patent: 4364165 (1982-12-01), Dickman et al.
patent: 4535528 (1985-08-01), Chen et al.
patent: 4666553 (1987-05-01), Blumenfeld et al.
patent: 4799992 (1989-01-01), Rao et al.
S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Lattice Press, Sunset Beach, CA (1986), pp. 189-191.
R. A. Levy and K. Nassau, "Viscous Behavior of Phosphosilicate and Borophosphosilicate Glasses in VLSI Processing", Solid State Technology (1986), pp. 123-230.

Affiliated with

Also associated with

Rating

Method of manufacturing a semiconductor device with a planar int does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a semiconductor device with a planar int, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device with a planar int will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1510017