Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Isolation by pn junction only
Reexamination Certificate
2005-05-31
2005-05-31
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Isolation by pn junction only
C438S529000
Reexamination Certificate
active
06900109
ABSTRACT:
A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the semiconductor device. The vertical MOSFET according to the invention includes an alternating-conductivity-type drain drift layer on an n+-type drain layer as a substrate. The alternating-conductivity-type drain drift layer is formed of n-type drift current path regions and p-type partition regions alternately arranged laterally with each other. The n-type drift current path regions and p-type partition regions extend in perpendicular to n+-type drain layer. Each p-type partition region is formed by vertically connecting p-type buried diffusion unit regions Up. The n-type drift current path regions are residual regions, left after connecting p-type buried diffusion unit regions Up, with the conductivity type thereof unchanged. The alternating-conductivity-type drain drift layer is formed by repeating the step of epitaxial layer growth and the step of implanting p-type impurity ions and by diffusing the impurity ions at once from the impurity sources located on multiple levels.
REFERENCES:
patent: 4754310 (1988-06-01), Coe
patent: 5141889 (1992-08-01), Terry et al.
patent: 5183769 (1993-02-01), Rutter et al.
patent: 5216275 (1993-06-01), Chen
patent: 5286655 (1994-02-01), Tsunoda
patent: 5292672 (1994-03-01), Akiyama et al.
patent: 5438215 (1995-08-01), Tihanyi
patent: 5798554 (1998-08-01), Grimaldi et al.
patent: 6081009 (2000-06-01), Neilson
patent: 6097063 (2000-08-01), Fujihira
patent: 6184555 (2001-02-01), Tihanyi et al.
patent: 6198141 (2001-03-01), Yamazaki et al.
patent: 6207994 (2001-03-01), Rumennik et al.
patent: 6274904 (2001-08-01), Tihanyi
patent: 6300171 (2001-10-01), Frisina
patent: 6307246 (2001-10-01), Nitta et al.
patent: 6475864 (2002-11-01), Sato et al.
patent: 6551909 (2003-04-01), Fujihira
patent: 6677626 (2004-01-01), Shindou et al.
patent: 2001/0028083 (2001-10-01), Onishi et al.
patent: 2001/0046739 (2001-11-01), Miyasaka et al.
patent: 0053854 (1986-02-01), None
patent: 54-22179 (1979-02-01), None
patent: 1-93169 (1989-04-01), None
patent: 401272158 (1989-10-01), None
patent: 3-105975 (1991-05-01), None
patent: 10-223896 (1998-08-01), None
patent: 2000-40822 (2000-02-01), None
“Theory of Semiconductor Superjunction Devices”; Tatsuhiko Fujihira; Jpn. J. Appl. Phys. vol. 36 (1997), Part 1 No. 10, Oct. 1997; pp. 6254-6262.
Fujihira Tatsuhiko
Iwamoto Susumu
Onishi Yasuhiko
Sato Takahiro
Fourson George
Fuji Electric & Co., Ltd.
Pham Thanh
Rossi, Kimms & McDowell
LandOfFree
Method of manufacturing a semiconductor device with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3406647