Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1997-06-04
1998-11-17
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438253, 438254, 438397, H01L 2120, H01L 218242
Patent
active
058375945
ABSTRACT:
Used nearer to a MOS transistor (25, 29(1), 29(2)) together with another capacitor electrode (39) with a dielectric film (37) interposed for use in a DRAM, a capacitor electrode is manufactured to include a conductor pole (53) and a tray-shaped conductor layer (55) which is held by the conductor pole and to include a plate portion (57) extended perpendicular to a pole axis and having a plate periphery and a peripheral portion (59) extended parallel to the pole axis from the plate periphery towards a pole end. Preferably, the tray-shaped conductor layer is held by the pole on a plurality of levels. A planar conductor layer may additionally be held at the pole end perpendicular to the pole axis. Word (41) and bit (49) lines are embedded in an insulator layer (43, 51) for the capacitor and the transistor.
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H. Watanabe, et al., "Hemispherical Grained Si Formation on in situ Phosphorus Doped Amorphous-Si Electrode for 256Mb DRAM's Capacitor", 8093 IEEE Transactions on Electron Devices 42(1995) Jul., No. 7, pp. 1247-1253.
Honma Ichiroh
Watanabe Hirohito
Bowers Jr. Charles L.
NEC Corporation
Thomas Toniae M.
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