Method of manufacturing a semiconductor device using SEG and a t

Details Method of manufacturing a semiconductor device using SEG and a t Method of manufacturing a semiconductor device using SEG and a t

1989-08-04

1990-11-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

148DIG26, 357 49, 437 63, 437 86, 437 99, 437978, H01L 2120

Patent

active

049701754

ABSTRACT:
A method of manufacturing a semiconductor device in which a silicon layer (8) is epitaxially grown on the surface of a doped monocrystalline semiconductor body (7), whereafter a connection is established between said semiconductor body (7) and a second semiconductor body (1) which is used as a supporting body, while at least one of the surfaces of the two bodies is firstly provided with an insulating layer (2,3) and a rigid connection is established between the bodies, whereafter the monocrystalline semiconductor body (7) is electrochemically etched away down to the epitaxially grown silicon layer (8), parts of the insulating layer (2,3) being removed prior to establishing the connection between the bodies (1,7), whereafter a layer of electrically conducting material (6) is deposited on the surface with a thickness which is larger than that of the insulating layer, whereafter a polishing treatment is performed at least down to the insulating layer.

REFERENCES:
patent: 3850707 (1974-11-01), Bestland
patent: 4530149 (1985-07-01), Jastrzebski et al.
patent: 4820653 (1989-04-01), Easter et al.
patent: 4849371 (1989-07-01), Hansen et al.
patent: 4851366 (1989-07-01), Blanchard
patent: 4879258 (1989-11-01), Fisher
patent: 4902641 (1990-02-01), Koury, Jr.
patent: 4908328 (1990-03-01), Hu et al.

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