Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2003-06-04
2004-04-20
Chaudhari, Chanda (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S465000
Reexamination Certificate
active
06723583
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device manufacturing method and a semiconductor technique. Particularly, the invention is concerned with a technique which is effective in its application to a semiconductor device having a small-sized package structure.
A CSP (Chip Size Package) or the like having an external package size almost equal to or slightly larger than that of a semiconductor chip permits a high-density packaging corresponding to bare chip packaging and is relatively low in its manufacturing cost. With these advantages, there is now an increasing demand for CSP in the field of small-sized, light-weight electronic devices such as portable information devices, digital cameras, and notebook type personal computers.
In connection with the CSP, various package forms are available. But there generally is adopted a Ball Grip Array (BGA) structure wherein solder bumps are attached to one side of a package substrate with a semiconductor chip mounted thereon and are reflow-soldered to a surface of a printed wiring board. Particularly, in the case of a thin multi-pin CSP, a TCP (Tape Carrier Package) type BGA (tape BGA) is most popular wherein a package substrate with a semiconductor chip mounted thereon is constituted by such an insulating tape as a polyimide tape. As to the TCP using an insulating tape as a package substrate, it is disclosed, for example, in Japanese Published Unexamined Patent Application No. Hei 7(1995)-321248.
SUMMARY OF THE INVENTION
However, the present inventor has found out that the following problems are involved in the above CSP technique using an insulating tape as a package substrate.
The problem is that it is difficult to apply the CSP technique to products for which high reliability is required. For example, this is because in the CSP structure using an insulating tape as a package substrate it is inevitably required that the temperature cyclicity after packaging be set lower than the user's request, which may be attributable to the material of the package substrate being polyimide, thus making it impossible to attain a further improvement of reliability.
The second problem is that the semiconductor device manufacturing cost is high. For example, this is because the polyimide tape as the material of the package substrate is expensive. Another reason is that in the manufacture of a CSP using an insulating tape as a package substrate, each individual semiconductor chip is sealed and that therefore the number of products obtained per unit area is small, thus leading to a high basic unit price.
In connection with the present invention the present inventor has searched prior art literatures from the standpoint of mold. As a result, for example in Japanese Published Unexamined Patent Application No. Hei 10(1998)-256286 there was found to be disclosed a technique wherein a coating layer is formed on an inner surface of a mold to effect mold release smoothly. In Japanese Published Unexamined Patent Application No. Hei 10(1998)-244556 is disclosed a technique of molding a resin package in a closely contacted state of a release film with an inner surface of a mold in order to facilitate removal of the resin package from the mold. In Japanese Published Unexamined Patent Application No. Hei 11(1999)-16930 is disclosed a technique of evacuating sheet to prevent creasing of the sheet at the time of molding using the sheet. In Japanese Published Unexamined Patent Application No. 2000-12578 is disclosed a technique of performing a transfer molding while mounting a large number of chips on a substrate. Further, in Japanese Published Unexamined Patent Application No. 2000-138246 is disclosed a mold of high versatility with an ejector pin attached thereto for each plural blocks.
It is an object of the present invention to provide a technique capable of improving the reliability of a semiconductor device.
It is another object of the present invention to provide a technique capable of reducing the cost of a semiconductor device.
The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
Out of the inventions disclosed herein, typical ones will be outlined below.
According to the present invention, a first substrate with plural semiconductor chips mounted on a first surface thereof is set within a mold, a film is interposed between an upper mold half of the mold and the first surface of the first substrate, the film is then vacuum-chucked to the upper mold, then in this state the plural semiconductor chips are together sealed with resin to form a seal member, and thereafter the first substrate and the seal member both released from the mold with use of the film cut into plural semiconductor devices.
According to the present invention, a first substrate with plural semiconductor chips mounted on a first surface thereof is set within a mold, a second surface lying on the back of the first surface of the first substrate is vacuum-chucked to a lower mold half of the mold, then in this state the plural semiconductor chips are together sealed with resin to form a seal member, and thereafter the first substrate and the seal member both released from the mold are cut into plural semiconductor devices.
According to the present invention, plural semiconductor chips mounted on a first main surface of a first substrate having a structure highly resistant to a thermal stress are together sealed to form a seal member, the seal member is then released from a mold used, and thereafter the first substrate and the seal member both released from the mold are cut into plural semiconductor devices.
According to the present invention, the above first substrate is constituted mainly by an insulating material of the same type as that used for a second substrate on which is mounted the first substrate.
According to the present invention, the above first substrate is constituted mainly by an insulating material equal in thermal expansion coefficient to a second substrate on which is mounted the first substrate.
According to the present invention, the above first and second substrates are constituted mainly by a glass-epoxy resin-based insulating material.
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English-Language Translation of JP 2000-138246, Published May 16, 2000, Patent Abstracts of Japan.
Hashizume Takanori
Ichitani Masahiro
Imura Kenichi
Matsuura Takao
Miwa Takashi
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