Method of manufacturing a semiconductor device using a main vern

Details Method of manufacturing a semiconductor device using a main vern Method of manufacturing a semiconductor device using a main vern

1989-11-27

1991-05-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 8, 356400, 356401, 430 5, 430311, 430312, H01L 2100, H01L 2102, H01L 2130, H01L 2166

Patent

active

050175149

ABSTRACT:
A semiconductor device has a device section and a peripheral section outside the device section. A main vernier pattern is formed in the peripheral section for inspecting finely an alignment state in a first direction, and a subsidiary vernier pattern is formed in the peripheral section near the main vernier pattern for inspecting coarsely an alignment state in a second direction at a right angle to the first direction.

REFERENCES:
patent: 4405238 (1983-09-01), Grobman et al.
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patent: 4547446 (1985-10-01), Tam
patent: 4600309 (1986-07-01), Fay
patent: 4606643 (1986-08-01), Tam
patent: 4610940 (1986-09-01), Araihara
patent: 4623257 (1986-11-01), Feather
patent: 4626907 (1986-12-01), Schedewie
patent: 4742233 (1988-05-01), Kuyel

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