Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2002-07-16
2004-07-27
Chambliss, Alonzo (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S126000, C438S127000, C029S841000, C029S855000, C029S856000
Reexamination Certificate
active
06767767
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device and more particularly to a technique which is effective in its application to a technique (MAP: Matrix Array Packaging method) of manufacturing plural semiconductor devices. According to this technique, a main surface side of a substrate with plural semiconductor chips (semiconductor elements) arranged thereon regularly in longitudinal and transverse directions is covered with a seal member (package) by block molding of an insulating resin and thereafter the substrate and the package superimposed one on the other are divided longitudinally and transversely to fabricate plural semiconductor devices.
As package forms of semiconductor devices adapted for the tendency to multi-function and higher density there are known, for example, BGA (Ball Grid Array) and CSP (Chip Size Package). As an example of a technique for fabricating such BGA and CSP there is known a semiconductor device manufacturing method comprising providing a wiring substrate, mounting a semiconductor chip (semiconductor element) at a predetermined position of a main surface of the wiring substrate, connecting electrodes on the semiconductor chip and wiring lines on the main surface of the wiring substrate with each other through electrically conductive wires, then covering the main surface side of the wiring substrate with an insulating sealing resin, and forming salient electrodes (bump electrodes) on a back surface of the wiring substrate, the salient electrodes being connected to the wiring lines.
For the purpose of reducing the semiconductor device manufacturing cost there has been adopted an MAP method comprising using a matrix type wiring substrate with product forming areas provided longitudinally and transversely in a lattice shape, mounting predetermined semiconductor chips in the product forming areas, respectively, of the matrix wiring substrate, thereafter connecting electrodes of the semiconductor chips and wiring lines on a main surface of the wiring substrate with each other through electrically conductive wires, then covering the whole of the main surface side of the matrix wiring substrate with an insulating sealing resin (block molding), forming salient electrodes (bump electrodes) on a back surface of the wiring substrate, the salient electrodes being connected to the wiring lines, and subsequently cutting the matrix wiring substrate and the package of the sealing resin longitudinally and transversely to fabricate plural semiconductor devices.
SUMMARY OF THE INVENTION
In the conventional transfer molding, including block molding, a cavity into which resin is injected, as well as gates and air vents both communicating with the cavity, are formed using a molding die.
In block molding, if an air vent is not formed correspondingly on an extension of semiconductor chips arranged in a column, the flow of resin in the cavity changes delicately, resulting in that voids remain on edges of the semiconductor chips which edges are hidden with respect to the resin flow, or unfilling of resin is apt to occur.
FIGS. 22
to
24
are schematic diagrams associated with a block molding method which the present inventor had studied before accomplishing the present invention. As shown in
FIG. 22
, a substrate
20
with semiconductor chips
10
arranged regularly on a main surface (an upper surface in the figure) thereof is held grippingly (mold clamping) between a lower mold
30
B and an upper mold
30
A of a molding die
30
, whereby there are formed a cavity
31
, as well as gates
32
and air vents
37
both communicating with the cavity
31
. Generally, a mating surface(s) (parting surface(s)) of the upper mold
30
A and/or the lower mold
30
B is (are) recessed for forming the cavity
31
, gates
32
and air vents
37
.
In the MAP method, a molding space (cavity) including all the semiconductor chips
10
fixed to the main surface of the substrate
20
is formed on the main surface side of the substrate. On one side of the cavity
31
are arranged plural gates
32
side by side, the gates
32
serving as flow paths for guiding molten resin
8
into the cavity
31
, while on another side (opposite side) opposite to the gates
32
are formed plural air vents
37
side by side, the air vents
37
serving as flow paths for guiding air
9
to the outside of the cavity
31
which air is forced out by the resin
8
flowing into the cavity
31
.
FIGS. 23 and 24
are schematic diagrams showing arrangement relations among the cavity
31
formed in the substrate
20
, the gates
32
and air vents
37
, and the semiconductor chips
10
mounted on the main surface of the substrate
20
. In
FIGS. 22
,
23
and
24
, which illustrate arrangement relations of the substrate
20
to the semiconductor chips
10
arranged on the substrate, wires for electrically connecting electrodes on the semiconductor chips
10
with wiring lines on the substrate
20
are not shown.
FIG. 23
shows such a positional relation between semiconductor chips and air vents as permits preventing the occurrence of voids and unfilling of resin. In
FIG. 23
, semiconductor chips
10
are arranged regularly in a lattice shape along both long and short sides of the substrate
20
which is quadrangular. In the example illustrated in the same figure, a total of twelve semiconductor chips
10
are arranged as three rows and four columns. That is, three semiconductor chips
10
are arranged in each column from gates
32
located on one side of the cavity
31
toward air vents
37
located on another side of the cavity
31
opposite to the gates
32
.
The air vents
37
are arranged correspondingly to the columns of semiconductor chips. The area between adjacent semiconductor chip columns, (chip-column-to-chip-column area), is wide as a resin flow path and encounters neither concave nor convex that obstruct the flow of resin, so that the flow velocity of resin flowing between adjacent chip columns becomes higher than that in a chip column area (a combined area of both areas where semiconductor chips are arranged and chip-to-chip areas in the columns of chips arranged in the direction in which the resin is injected). Consequently, the resin arrives so much earlier at a terminal end of the substrate
20
where the air vents
37
are arranged. Therefore, the air vents
37
are deviated from the extension of each chip-column-to-chip-column area and are arranged correspondingly to the extensions of the chip column areas.
FIG. 24
is a schematic diagram showing a substrate
20
as clamped to the molding die
30
illustrated in
FIG. 23
, the substrate
20
having a different arrangement of semiconductor chips. On a main surface of this substrate
20
are arranged semiconductor chips
10
regularly in seven columns and four rows. Since the air vents
37
are formed by the molding die
30
, their positions do not always correspond to positions located on the extensions of chip column areas and air vents located on the extensions of chip-column-to-chip-column areas are stopped up with resin and fail to function the moment the resin reaches the terminal end of the cavity past the chip-column-to-chip-column areas. In the portions where air vents are not provided on the extensions of chip-column-to-chip-column areas, the resin passing between adjacent chip-column-to-chip-column areas involves remaining air therein and generates voids upon arrival at the terminal end of the cavity.
For solving such a problem, that is, for forming air vents correspondingly to chip columns, it is necessary to provide molding dies correspondingly to various substrates, with consequent increase of the mold cost and hence increase in the cost of the semiconductor device manufactured by the MAP method.
It is an object of the present invention to provide a semiconductor device manufacturing method in accordance with an MAP method which can reduce the mold cost.
It is another object of the present invention to provide a semiconductor device manufacturing method in accordance with an MAP me
Hayashida Tetsuya
Kasai Norihiko
Chambliss Alonzo
Miles & Stockbridge P.C.
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